MPC8540 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MPC8540

Integrated Processor Hardware Specifications

Freescale Semiconductor 

RESET Initialization

4.3 RapidIO Transmit Clock Input Timing

Table 9 provides the RapidIO transmit clock input (RIO_TX_CLK_IN) AC timing specifications for the

MPC8540.

Table 9. RIO_TX_CLK_IN AC Timing Specifications

Parameter/Condition

Symbol

Min Typical Max

Unit

RIO_TX_CLK_IN frequency

fRCLK

125

—

—

MHz

RIO_TX_CLK_IN cycle time

tRCLK

—

—

8

ns

RIO_TX_CLK_IN duty cycle

tRCLKH/tRCLK

48

—

52

%

Notes:

1. Requires ±100 ppm long term frequency stability. Timing is guaranteed by design and characterization.

Notes

1

4.4 Real Time Clock Timing

Table 10 provides the real time clock (RTC) AC timing specifications for the MPC8540.

Table 10. RTC AC Timing Specifications

Parameter/Condition

RTC clock high time

RTC clock low time

Symbol

tRTCH

tRTCL

Min

2x

tCCB_CLK

2x

tCCB_CLK

Typical

—

—

Max

—

—

Unit

ns

ns

Notes

5 RESET Initialization

This section describes the AC electrical specifications for the RESET initialization timing requirements of

the MPC8540. Table 7 provides the RESET initialization AC timing specifications for the MPC8540.

Table 11. RESET Initialization Timing Specifications

Parameter/Condition

Min

Required assertion time of HRESET

100

Minimum assertion time for SRESET

512

PLL input setup time with stable SYSCLK before

100

HRESET negation

Input setup time for POR configs (other than PLL config)

4

with respect to negation of HRESET

Input hold time for POR configs (including PLL config)

2

with respect to negation of HRESET

Max

Unit

Notes

—

μs

—

SYSCLKs

1

—

μs

—

SYSCLKs

1

—

SYSCLKs

1

MPC8540 Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

15

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