RM7065A-350T View Datasheet(PDF) - PMC-Sierra

Part Name

Description

Manufacturer

RM7065A-350T

RM7065A™ Microprocessor with On-Chip Secondary Cache

PMC-Sierra 

RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet

Preliminary

create special purpose maps; for example, an entire frame buffer can be memory mapped using

only one TLB entry.

The second mechanism controls the replacement algorithm when a TLB miss occurs. The

RM7065A provides a random replacement algorithm to select a TLB entry to be written with a

new mapping. However, the processor also provides a mechanism whereby a system specific

number of mappings can be locked into the TLB, thereby avoiding random replacement. This

mechanism uses the CP0 Wired register and allows the operating system to guarantee that certain

pages are always mapped for performance reasons and to avoid a deadlock condition. This

mechanism also facilitates the design of real-time systems by allowing deterministic access to

critical software.

The JTLB also contains information that controls the cache coherency protocol for each page.

Specifically, each page has attribute bits to determine whether the coherency algorithm is:

• uncached

• write-back

• write-through with write-allocate

• write-through without write-allocate

• write-back with secondary bypass

Note that both of the write-through protocols bypass the secondary cache since it does not support

writes of less than a complete cache line.

These protocols are used for both code and data on the RM7065A with data using write-back or

write-through depending on the application. The write-through modes support the same efficient

frame buffer handling as the RM5200 Family.

4.14 Instruction TLB

The RM7065A uses a 4-entry instruction TLB (ITLB). The ITLB offers the following advantages;

• Minimizes contention for the JTLB

• Eliminates the critical path of translating through a large associative array

• Allows instruction address and data address translations to occur in parallel

• Saves power

Each ITLB entry maps a 4 KB page. The ITLB improves performance by allowing instruction

address translation to occur in parallel with data address translation. When a miss occurs on an

instruction address translation by the ITLB, the least-recently used ITLB entry is filled from the

JTLB. The operation of the ITLB is completely transparent to the user.

4.15 Data TLB

The RM7065A uses a 4-entry data TLB (DTLB) for the same reasons cited above for the ITLB.

Each DTLB entry maps a 4 KB page. The DTLB improves performance by allowing data address

translation to occur in parallel with instruction address translation. When a miss occurs on a data

address translation, the DTLB is filled from the JTLB. The DTLB refill is pseudo-LRU; the least

recently used entry of the least recently used pair of entries is filled. The operation of the DTLB is

completely transparent to the user.

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

21

Document ID: PMC-2010145, Issue 2

Share Link: