RM7065A-350T View Datasheet(PDF) - PMC-Sierra
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RM7065A-350T Datasheet PDF : 52 Pages
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RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
The RM7065A cache attributes for the instruction, data, internal secondary caches are summarized
in Table 6.
Table 6 Cache Attributes
Attribute Instruction
Size
16KB
Associativity 4-way
Replacement cyclic
Algorithm
Line size
32 byte
Index
vAddr11..0
Tag
pAddr35..12
Write policy n.a.
read policy n.a.
read order critical word first
write order
miss restart
following:
Parity
NA
complete line
per word
Data
16KB
4-way
cyclic
Secondary
256KB
4-way
cyclic
32 byte
32 byte
vAddr11..0
pAddr15..0
pAddr35..12
pAddr35..16
write-back,
block write-
write-through back, bypass
non-blocking (2 non-blocking
outstanding) (data only, 2
outstanding)
critical word first critical word
first
sequential
sequential
first double (if n.a.
waiting for data)
per byte
per
doubleword
4.21 Cache Locking
The RM7065A allows critical code or data fragments to be locked into the primary and secondary
caches. The user has complete control over the locking function. For instruction and data
fragments in the primary caches, locking is accomplished by setting either or both of the cache
lock enable bits and specifying the set in the CP0 ECC register, then executing either a load
instruction for data, or a Fill_I cache operation for instructions.
Only sets A and B within each cache can be locked. Locking within the secondary works
identically to the primaries using a separate secondary lock enable bit and the same set selection
field. As with the primaries, only sets A and B can be locked. Table 7 summarizes the cache
locking capabilities.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
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Document ID: PMC-2010145, Issue 2
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