MT41J128M View Datasheet(PDF) - Micron Technology
Part Name
Description
Manufacturer
MT41J128M Datasheet PDF : 214 Pages
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1Gb: x4, x8, x16 DDR3 SDRAM
Ball Assignments and Descriptions
Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued)
Symbol
DQ0, DQ1, DQ2,
DQ3, DQ4, DQ5,
DQ6, DQ7
DQS, DQS#
TDQS, TDQS#
VDD
VDDQ
VREFCA
VREFDQ
VSS
VSSQ
ZQ
NC
NF
Type
I/O
Description
Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are
referenced to VREFDQ.
I/O
Output
Supply
Supply
Supply
Supply
Supply
Supply
Reference
–
–
Data strobe: Output with read data. Edge-aligned with read data. Input with write
data. Center-aligned to write data.
Termination data strobe: Applies to the x8 configuration only. When TDQS is
enabled, DM is disabled, and the TDQS and TDQS# balls provide termination resist-
ance.
Power supply: 1.5V ±0.075V.
DQ power supply: 1.5V ±0.075V. Isolated on the device for improved noise immuni-
ty.
Reference voltage for control, command, and address: VREFCA must be
maintained at all times (including self refresh) for proper device operation.
Reference voltage for data: VREFDQ must be maintained at all times (excluding self
refresh) for proper device operation.
Ground.
DQ ground: Isolated on the device for improved noise immunity.
External reference ball for output drive calibration: This ball is tied to an
external 240Ω resistor (RZQ), which is tied to VSSQ.
No connect: These balls should be left unconnected (the ball has no connection to
the DRAM or to other balls).
No function: When configured as a x4 device, these balls are NF. When configured as
a x8 device, these balls are defined as TDQS#, DQ[7:4].
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
20
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
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