MT48LC1M16A1 View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT48LC1M16A1

SYNCHRONOUS DRAM

Micron Technology 

CLOCK SUSPEND MODE 1

T0

CLK

T1

tCK

T2

tCL

tCH

tCKS tCKH

CKE

tCKS tCKH

tCMS tCMH

COMMAND

READ

NOP

NOP

DQM3

A0-A9

tAS tAH

COLUMN m

(A0 - A7)2

tAS tAH

tCMS tCMH

A10

tAS tAH

BA

BANK

tAC

DQ

tLZ

T3

T4

NOP

tAC

tOH

DOUT m

T5

NOP

tHZ

DOUT m + 1

T6

NOP

T7

WRITE

COLUMN e

(A0 - A7)2

BANK

tDS tDH

DIN e

16Mb: x16

IT SDRAM

T8

T9

NOP

DIN e + 1

DON’T CARE

UNDEFINED

TIMING PARAMETERS

SYMBOL*

tAC (3)

tAC (2)

tAC (1)

tAH

tAS

tCH

tCL

tCK (3)

tCK (2)

tCK (1)

tCKH

-6

MIN MAX

5.5

8

18

1

2

2.5

2.5

6

8

20

1

-7

MIN MAX

5.5

8.5

22

1

2

2.75

2.75

7

10

25

1

-8A

MIN MAX

6

9

22

1

2

3

3

8

13

25

1

UNITS

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

SYMBOL*

tCKS

tCMH

tCMS

tDH

tDS

tHZ (3)

tHZ (2)

tHZ (1)

tLZ

tOH

-6

MIN MAX

2

1

2

1

2

5.5

6

18

1

1.5

-7

MIN MAX

2

1

2

1

2

5.5

8.5

22

1

1.5

-8A

MIN MAX

2

1

2

1

2

6

9

22

1

1.5

UNITS

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and AUTO PRECHARGE is disabled.

2. A8 and A9 = “Don’t Care.”

3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.

16Mb: x16 IT SDRAM

16MSDRAMx16IT.p65 – Rev. 5/99

36

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©1999, Micron Technology, Inc.

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