MT48LC1M16A1 View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT48LC1M16A1

SYNCHRONOUS DRAM

Micron Technology 

T0

CLK

tCK

CKE

tCKS tCKH

tCMS tCMH

COMMAND PRECHARGE

DQM1

tAS tAH

ADDRESS

BANK(S)

High-Z

DQ

Precharge all

active banks.

T1

tCH

SELF REFRESH MODE

T2

tCL

((

))

tCKS

((

> tRAS ) )

Tn + 1

((

))

( ( To + 1

))

((

))

((

))

((

))

tCKS

NOP

((

AUTO

))

REFRESH

((

))

((

))

((

))

((

))

NOP ( (

))

((

))

((

))

((

((

))

))

((

((

))

))

((

((

))

))

tRP

tXSR

Enter self

refresh mode.

Exit self refresh mode.

(Restart refresh time base.)

CLK stable prior to exiting

self refresh mode.

16Mb: x16

IT SDRAM

To + 2

AUTO

REFRESH

DON’T CARE

UNDEFINED

TIMING PARAMETERS

SYMBOL*

tAH

tAS

tCH

tCL

tCK (3)

tCK (2)

tCK (1)

-6

MIN MAX

1

2

2.5

2.5

6

8

20

-7

MIN MAX

1

2

2.75

2.75

7

10

25

-8A

MIN MAX

1

2

3

3

8

13

25

UNITS

ns

ns

ns

ns

ns

ns

ns

SYMBOL*

tCKH

tCKS

tCMH

tCMS

tRAS

tRP

tXSR

-6

MIN MAX

1

2

1

2

42 120,000

18

80

-7

MIN MAX

1

2

1

2

42 120,000

21

80

-8A

MIN MAX UNITS

1

ns

2

ns

1

ns

2

ns

48 120,000 ns

24

ns

80

ns

*CAS latency indicated in parentheses.

NOTE: 1. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.

16Mb: x16 IT SDRAM

16MSDRAMx16IT.p65 – Rev. 5/99

38

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©1999, Micron Technology, Inc.

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