MT48LC1M16A1 View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT48LC1M16A1

SYNCHRONOUS DRAM

Micron Technology 

16Mb: x16

IT SDRAM

Fixed-length or full-page WRITE bursts can be trun-

cated with the BURST TERMINATE command. When

truncating a WRITE burst, the input data applied

coincident with the BURST TERMINATE command

will be ignored. The last data written (provided that

DQM is LOW at that time) will be the input data

applied one clock previous to the BURST TERMINATE

command. This is shown in Figure 19, where data n is

the last desired data element of a longer burst.

T0

T1

T2

CLK

COMMAND

WRITE

BURST

TERMINATE

Next

Command

ADDRESS

BANK,

COL n

(Address)

DIN

DQ

n

(Data)

NOTE: DQMs are low

Figure 19

Terminating a WRITE Burst

CLK

CKE HIGH

PRECHARGE

The PRECHARGE command is used to deactivate

the open row in a particular bank or the open row in

all banks (see Figure 20). The bank(s) will be available

for a subsequent row access some specified time (tRP)

after the PRECHARGE command is issued. Input A10

determines whether one or all banks are to be

precharged, and in the case where only one bank is to

be precharged, input BA selects the bank. When all

banks are to be precharged, input BA is treated as

“Don’t Care.” Once a bank has been precharged, it is in

the idle state and must be activated prior to any READ

or WRITE commands being issued to that bank.

POWER-DOWN

POWER-DOWN occurs if CKE is registered LOW

coincident with a NOP or COMMAND INHIBIT, when

no accesses are in progress (see Figure 21). If POWER-

DOWN occurs when all banks are idle, this mode is

referred to as precharge power-down; if power-down

occurs when there is a row active in either bank, this

mode is referred to as active power-down. Entering

power-down deactivates the input and output buff-

ers, excluding CKE, for maximum power savings while

in standby. The device may not remain in the power-

down state longer than the refresh period (64ms) since

no refresh operations are performed in this mode.

The power-down state is exited by registering a NOP

or COMMAND INHIBIT and CKE HIGH at the desired

clock edge (meeting tCKS).

CS#

RAS#

CAS#

WE#

A0-A9

A10

BA

BANK 0 and 1

BANK 0 or 1

BANK 1

BANK 0

Figure 20

PRECHARGE Command

CLK

tCKS

CKE

COMMAND

NOP

All banks idle

((

))

((

))

< tCKS

((

))

((

))

((

NOP

))

Input buffers gated off

Enter POWER-

DOWN mode

Exit POWER-

DOWN mode

Figure 21

POWER-DOWN

ACTIVE

tRCD

tRAS

tRC

DON’T CARE

16Mb: x16 IT SDRAM

16MSDRAMx16IT.p65 – Rev. 5/99

21

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©1999, Micron Technology, Inc.

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