MT48LC16M8A2TG-7ELIT View Datasheet(PDF) - Micron Technology
Part Name
Description
Manufacturer
MT48LC16M8A2TG-7ELIT Datasheet PDF : 59 Pages
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128Mb: x4, x8, x16
SDRAM
SINGLE WRITE – WITHOUT AUTO PRECHARGE 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP 4
NOP 4
PRECHARGE
NOP
ACTIVE
NOP
DQM /
DQML, DQMH
A0-A9, A11
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
ROW
tAS tAH
BANK
tCMS tCMH
COLUMN m 3
DISABLE AUTO PRECHARGE
BANK
ALL BANKS
SINGLE BANK
BANK
ROW
BANK
tDS tDH
DQ
DIN m
tRCD
t WR 2
tRP
tRAS
tRC
DON’T CARE
TIMING PARAMETERS
SYMBOL*
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCKH
tCKS
tCMH
-7E
MIN MAX
0.8
1.5
2.5
2.5
7
7.5
0.8
1.5
0.8
-75
MIN MAX
0.8
1.5
2.5
2.5
7.5
10
0.8
1.5
0.8
-8E
MIN MAX
1
2
3
3
8
10
1
2
1
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL*
tCMS
tDH
tDS
tRAS
tRC
tRCD
tRP
tWR
-7E
MIN MAX
1.5
0.8
1.5
37 120,000
60
15
15
14
-75
MIN MAX
1.5
0.8
1.5
44 120,000
66
20
20
15
-8E
MIN MAX UNITS
2
ns
1
ns
2
ns
50 120,000 ns
70
ns
20
ns
20
ns
15
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
3. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
4. PRECHARGE command not allowed else tRAS would be violated.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
51
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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