MT48LC16M8A2TG-7ELIT View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT48LC16M8A2TG-7ELIT

SYNCHRONOUS DRAM

Micron Technology 

128Mb: x4, x8, x16

SDRAM

WRITE – FULL-PAGE BURST

T0

CLK

T1

tCL

tCH

tCKS tCKH

CKE

tCMS tCMH

COMMAND

ACTIVE

NOP

T2

tCK

WRITE

DQM /

DQML, DQMH

A0-A9, A11

tAS tAH

ROW

tAS tAH

A10

ROW

BA0, BA1

tAS tAH

BANK

tCMS tCMH

COLUMN m1

BANK

DQ

tRCD

tDS tDH

DIN m

T3

NOP

T4

NOP

T5

( ( Tn + 1

))

((

))

((

))

((

))

((

))

NOP ( (

))

NOP

((

))

((

))

Tn + 2

Tn + 3

BURST TERM

NOP

((

))

((

))

((

))

((

))

((

))

((

))

tDS tDH

DIN m + 1

tDS tDH

DIN m + 2

tDS tDH

((

))

DIN m + 3 ( (

))

tDS tDH

DIN m - 1

512 (x16) locations within same row

1,024 (x8) locations within same row

2,048 (x4) locations within same row

Full-page burst does not

self-terminate. Can use

BURST TERMINATE

command to stop.2, 3

Full page completed

DON’T CARE

TIMING PARAMETERS

SYMBOL*

tAH

tAS

tCH

tCL

tCK (3)

tCK (2)

tCKH

-7E

MIN MAX

0.8

1.5

2.5

2.5

7

7.5

0.8

-75

MIN MAX

0.8

1.5

2.5

2.5

7.5

10

0.8

-8E

MIN MAX

1

2

3

3

8

10

1

UNITS

ns

ns

ns

ns

ns

ns

ns

*CAS latency indicated in parentheses.

NOTE: 1. x16: A9 and A11 = “Don’t Care”

x8: A11 = “Don’t Care”

2. tWR must be satisfied prior to PRECHARGE command.

3. Page left open; no tRP.

SYMBOL*

tCKS

tCMH

tCMS

tDH

tDS

tRCD

-7E

MIN MAX

1.5

0.8

1.5

0.8

1.5

15

-75

MIN MAX

1.5

0.8

1.5

0.8

1.5

20

-8E

MIN MAX

2

1

2

1

2

20

UNITS

ns

ns

ns

ns

ns

ns

128Mb: x4, x8, x16 SDRAM

128MSDRAM_E.p65 – Rev. E; Pub. 1/02

54

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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