MT48LC8M32B2 View Datasheet(PDF) - Micron Technology
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Description
Manufacturer
MT48LC8M32B2 Datasheet PDF : 55 Pages
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PRELIMINARY
256Mb: x32
SDRAM
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropri-
ate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to trun-
cate fixed-length or full-page bursts.
Full-page READ bursts can be truncated with the
BURST TERMINATE command, and fixed-length READ
bursts may be truncated with a BURST TERMINATE
command, provided that auto precharge was not acti-
vated. The BURST TERMINATE command should be
issued x cycles before the clock edge at which the last
desired data element is valid, where x equals the CAS
latency minus one. This is shown in Figure 12 for each
possible CAS latency; data element n + 3 is the last
desired data element of a longer burst.
T0
CLK
Figure 12
Terminating a READ Burst
T1
T2
T3
T4
T5
T6
COMMAND
READ
NOP
NOP
ADDRESS
BANK,
COL n
NOP
BURST
NOP
NOP
TERMINATE
X = 0 cycles
DQ
DOUT
n
CAS Latency = 1
DOUT
n+1
DOUT
n+2
DOUT
n+3
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
NOP
NOP
ADDRESS
BANK,
COL n
NOP
BURST
NOP
NOP
TERMINATE
X = 1 cycle
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
NOP
NOP
ADDRESS
BANK,
COL n
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
DQ
CAS Latency = 3
NOTE: DQM is LOW.
NOP
BURST
NOP
TERMINATE
NOP
NOP
X = 2 cycles
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
21
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©2003 Micron Technology, Inc.
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