PC8240 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
PC8240 Datasheet PDF : 42 Pages
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PC8240
2. All PCI signals are measured from OVdd/2 of the rising edge of PCI_SYNC_IN to 0.4*OVdd of the signal in question for 3.3V
PCI signaling levels. See Figure 11.
3. Input timings are measured at the pin.
4. tCLK is the time of one SDRAM_SYNC_IN clock cycle.
5. All mode select input signals specifications are measured from the TTL level (0.8 or 2.0V) of the signal in question to the VM
= 1.4V of the rising edge of the HRST_CPU/HRST_CTRL signal. See Figure 12.
Figure 10. Input – Output Timing Diagram Referenced to SDRAM_SYNC_IN
PCI_SYNC_IN
SDRAM_SYNC_IN
VM
VM
shown in 2:1 mode
MEMORY
INPUTS/OUTPUTS
10b-d
11a
2.0V
12b-d
2.0V
Input Timing
0.8V
0.8V
VM = Midpoint Voltage (1.4V)
Figure 11. Input – Output Timing Diagram Referenced to PCI_SYNC_IN
PCI_SYNC_IN
OVdd/2
OVdd/2
VM
13b
14b
Output Timing
OVdd/2
PCI
INPUTS/OUTPUTS
10a
11a
0.4*OVdd
Input Timing
Figure 12. Input Timing Diagram for Mode Select Signals
HRST_CPU/HRST_CTRL
13a
12a
14a
0.615*OVdd
0.285*OVdd
Output Timing
VM
MODE PINS
10e
11b
2.0V
0.8V
VM = Midpoint Voltage (1.4V)
21
2149A–HIREL–05/02
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