PC8240 View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

PC8240

Integrated Processor Family

Atmel Corporation 

PC8240

4. Specified at a nominal 50 pF load.

5. DFDR is the decimal divider number indexed by FDR[5:0] value. Refer to the two-wire interface Interface chapter’s Serial

Bit Clock Frequency Divider Selections table. FDR[x] refers to the Frequency Divider Register I2CFDR bit x. N is equal to a

variable number that would make the result of the divide (Data Hold Time value) equal to a number less than 16. M is equal

to a variable number that would make the result of the divide (Data Hold Time value) equal to a number less than 9.

Figure 15. Two-wire Interface Timing Diagram I

2

SCL

VM

1

VM

6

4

SDA

Figure 16. Two-wire Interface Timing Diagram II

5

SCL

VM

3

VH

VL

8

9

SDA

Figure 17. Two-wire Interface Timing Diagram III

DFFSR FILTER CLK (1)

SDA

7

INPUT DATA VALID

Note 1: DFFSR Filter Clock is the SDRAM_CLK clock times DFFSR value.

27

2149A–HIREL–05/02

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