PC8240 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
PC8240 Datasheet PDF : 42 Pages
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Figure 19. EPIC Serial Interrupt Mode Output Timing Diagram
sys_logic_clk3
VM
VM
3
4
S_CLK
VM
VM
S_FRAME
S_RST
5
VM
Figure 20. EPIC Serial Interrupt Mode Input Timing Diagram
S_CLK
6
S_INT
VM
4
VM
VM
7
PC8240
IEEE 1149.1 (JTAG) AC Timing Table 17 provides the JTAG AC timing specifications for the PC8240 while in the JTAG
Specifications
operating mode.
At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V ± 5%
and LVdd = 3.3V ± 5%
Table 17. JTAG AC Timing Specifications (Independent of PCI_SYNC_IN)
Num Characteristics(4)
Min
Max
Unit
TCK Frequency of Operation
0
25
MHz
1 TCK Cycle Time
40
–
ns
2 TCK Clock Pulse Width Measured at 1.5V
20
–
ns
3 TCK Rise and Fall Times
0
3
ns
4 TRST_ Setup Time to TCK Falling Edge
10
–
ns
5 TRST_ Assert Time
10
–
ns
6 Input Data Setup Time
5
–
ns
7 Input Data Hold Time
15
–
ns
8 TCK to Output Data Valid
0
30
ns
9 TCK to Output High Impedance
0
30
ns
Notes
(1)
(2)
(2)
(3)
(3)
29
2149A–HIREL–05/02
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