S25FL127S View Datasheet(PDF) - Spansion Inc.
Part Name
Description
Manufacturer
S25FL127S Datasheet PDF : 131 Pages
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Data Sheet (Preliminary)
3.6
3.7
3.8
3.9
Serial Input (SI) / IO0
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data
to be programmed. Values are latched on the rising edge of serial SCK clock signal.
SI becomes IO0 - an input and output during Dual and Quad commands for receiving instructions, addresses,
and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out
data (on the falling edge of SCK).
Serial Output (SO) / IO1
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of
the serial SCK clock signal.
SO becomes IO1 - an input and output during Dual and Quad commands for receiving addresses, and data to
be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the
falling edge of SCK.
Write Protect (WP#) / IO2
When WP# is driven Low (VIL), during a WRR command and while the Status Register Write Disable (SRWD)
bit of the Status Register is set to a 1, it is not possible to write to the Status and Configuration Registers. This
prevents any alteration of the Block Protect (BP2, BP1, BP0) and TBPROT bits of the Status Register. As a
consequence, all the data bytes in the memory area that are protected by the Block Protect and TBPROT
bits, are also hardware protected against data modification if WP# is Low during a WRR command.
The WP# function is not available when the Quad mode is enabled (CR[1]=1). The WP# function is replaced
by IO2 for input and output during Quad mode for receiving addresses, and data to be programmed (values
are latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK).
WP# has an internal pull-up resistor; when unconnected, WP# is at VIH and may be left unconnected in the
host system if not used for Quad mode.
Hold (HOLD#) / IO3 / RESET#
The Hold (HOLD#) signal is used to pause any serial communications with the device without deselecting the
device or stopping the serial clock. The HOLD# input and function is available when enabled by a
configuration bit SR2[5] =0.
To enter the Hold condition, the device must be selected by driving the CS# input to the logic low state. It is
recommended that the user keep the CS# input low state during the entire duration of the Hold condition. This
is to ensure that the state of the interface logic remains unchanged from the moment of entering the Hold
condition. If the CS# input is driven to the logic high state while the device is in the Hold condition, the
interface logic of the device will be reset. To restart communication with the device, it is necessary to drive
HOLD# to the logic high state while driving the CS# signal into the logic low state. This prevents the device
from going back into the Hold condition.
The Hold condition starts on the falling edge of the Hold (HOLD#) signal, provided that this coincides with
SCK being at the logic low state. If the falling edge does not coincide with the SCK signal being at the logic
low state, the Hold condition starts whenever the SCK signal reaches the logic low state. Taking the HOLD#
signal to the logic low state does not terminate any Write, Program or Erase operation that is currently in
progress.
During the Hold condition, SO is in high impedance and both the SI and SCK input are Don't Care.
The Hold condition ends on the rising edge of the Hold (HOLD#) signal, provided that this coincides with the
SCK signal being at the logic low state. If the rising edge does not coincide with the SCK signal being at the
logic low state, the Hold condition ends whenever the SCK signal reaches the logic low state.
The HOLD# function is not available when the Quad mode is enabled (CR1[1] =1). The Hold function is
replaced by IO3 for input and output during Quad mode for receiving addresses, and data to be programmed
(values are latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK.
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S25FL127S
S25FL127S_00_02 April 25, 2013
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