S25FL127S View Datasheet(PDF) - Spansion Inc.
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S25FL127S Datasheet PDF : 131 Pages
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Data Sheet (Preliminary)
6.3.2
Separate RESET# Input Initiated Hardware (Warm) Reset
When the RESET# input transitions from VIH to VIL for > tRP the device will reset register states in the same
manner as power-on reset but, does not go through the full reset process that is performed during POR. The
hardware reset process requires a period of tRPH to complete. If the POR process did not complete correctly
for any reason during power-up (tPU), RESET# going low will initiate the full POR process instead of the
hardware reset process and will require tPU to complete the POR process.
A separate RESET# input is available only in BGA package options. The RESET# input has an internal pullup
to VCC and may be left unconnected. The RESET command is independent of the state of RESET#. If
RESET# is high or unconnected, and the RESET instruction is issued, the device will perform software reset.
The RESET# input provides a hardware method of resetting the flash memory device to standby state.
RESET# must be high for tRS following tPU or tRPH, before going low again to initiate a hardware reset.
When RESET# is driven low for at least a minimum period of time (tRP), the device terminates any
operation in progress, makes all outputs high impedance, and ignores all read/write commands for the
duration of tRPH. The device resets the interface to standby state.
If CS# is low at the time RESET# is asserted, CS# must return high during tRPH before it can be asserted
low again after tRH.
Table 6.3 Hardware Reset Parameters
Parameter
tRS
tRPH
tRP
tRP
tRH
Description
Reset Setup -Prior Reset end and RESET# high before RESET# low
Reset Pulse Hold - RESET# low to CS# low
RESET# Pulse Width
RESET# Pulse Width (only when AutoBoot enabled)
Reset Hold - RESET# high before CS# low
Limit
Min
Min
Min
Max
Min
Time
50
35
200
5
50
Unit
ns
µs
ns
µs
ns
Notes:
1. RESET# Low is ignored during Power-up (tPU). If Reset# is asserted during the end of tPU, the device will remain in the reset state and
tRH will determine when CS# may go Low.
2. Sum of tRP and tRH must be equal to or greater than tRPH.
RESET#
CS#
Figure 6.7 Separate RESET# Input Initiated Hardware Reset
Any prior reset
tRPH
tRH
tRS
tRP
tRH
tRPH
6.3.3
IO3 / RESET# Input Initiated Hardware (Warm) Reset
The IO3 / RESET# signal functions as a RESET# input when enabled by SR2[5]=1 and CS# is high for more
than tCS time or when Quad Mode is not enabled (CR1V[1]=0). The IO3 RESET# input provides a hardware
method of resetting the flash memory device to standby state. The IO3 / RESET# input has an internal pull-up
to VCC and may be left unconnected if Quad mode is not used.
When the IO3 / RESET# feature and Quad mode are both enabled, IO3 / RESET# is ignored for tCS following
CS# going high, to avoid an unintended Reset operation. This allows some time for the memory or host
system to actively drive IO3 / RESET# to a valid level following the end of a transfer. Following the end of a
Quad I/O read the memory will actively drive IO3 high before disabling the output during tDIS. Following a
transfer in which IO3 was used to transfer data to the memory, e.g. the QPP command, the host system is
responsible for driving IO3 high before disabling the host IO3 output. The integrated pull-up on IO3 will then
April 25, 2013 S25FL127S_00_02
S25FL127S
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