S5L9284 View Datasheet(PDF) - Samsung
Part Name
Description
Manufacturer
S5L9284 Datasheet PDF : 24 Pages
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DIGITAL SIGNAL PROCESSOR
S5L9284D
CNTL-Z Register
It is a register to control the zero cross mute of audio data, the phase terminal control, the phase servo and having
CRCF data in SQDT or not.
ZCMT
HIPD
NCLV
CRCQ
DATA
D3
D2
D1
D0
DATA = 0
Zero cross mute is OFF
It operates phase normally
Phase servo is acted by frame sync
SQDT output except for SQOK
DATA = 1
Zero cross mute is ON
The phase becomes “L” to “Hi-Z”
Phase servo is controlled by base counter
SQDT = CRCF when S0S1 = “H”
CNTL-S Register
It is a register to control frame sync protection and attenuation.
FSEM
0
0
1
1
FSEL
0
1
0
1
FRAME
2
4
8
13
WSEL
0
1
CLOCK
±3
±7
ATTM MUTE
dB
0
0
0
0
1
−∞
1
0
− 12
1
1
− 12
CNTL-L, U Register
After the number of tracks that must be counted is input from micom , the data is loaded to the tracking counter by
the CNTL-L, U register.
CNTL-W Register
It is a register to control CLV-servo.
DATA DATA = 0 DATA = 1
COM
D3
XTFR/4 and PBFR/4
WB
D2
XTFR/32
XTFR/16
WP
D1
XTFR/4
XTFR/2
GAIN
D0
−12dB
0dB
Comment
Phase comparison frequency control during Phase - mode
Bottom hold period control during speed or HSpeed-mode
Peak hold period control during Speed-mode
SMDP gain control during Speed or HSpeed-Mode
11
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