SST25VF040B View Datasheet(PDF) - Silicon Storage Technology
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Description
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SST25VF040B Datasheet PDF : 33 Pages
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Data Sheet
32-KByte and 64-KByte Block-Erase
The 32-KByte Block-Erase instruction clears all bits in the
selected 32 KByte block to FFH. A Block-Erase instruction
applied to a protected memory area will be ignored. The
64-KByte Block-Erase instruction clears all bits in the
selected 64 KByte block to FFH. A Block-Erase instruction
applied to a protected memory area will be ignored. Prior to
any Write operation, the Write-Enable (WREN) instruction
must be executed. CE# must remain active low for the
duration of any command sequence. The 32-Kbyte Block-
Erase instruction is initiated by executing an 8-bit com-
mand, 52H, followed by address bits [A23-A0]. Address bits
[AMS-A15] (AMS = Most Significant Address) are used to
4 Mbit SPI Serial Flash
SST25VF040B
determine block address (BAX), remaining address bits can
be VIL or VIH. CE# must be driven high before the instruction
is executed. The 64-Kbyte Block-Erase instruction is initi-
ated by executing an 8-bit command D8H, followed by
address bits [A23-A0]. Address bits [AMS-A15] are used to
determine block address (BAX), remaining address bits can
be VIL or VIH. CE# must be driven high before the instruction
is executed. The user may poll the Busy bit in the software
status register or wait TBE for the completion of the internal
self-timed 32-KByte Block-Erase or 64-KByte Block-Erase
cycles. See Figures 13 and 14 for the 32-KByte Block-
Erase and 64-KByte Block-Erase sequences.
CE#
MODE 3
SCK MODE 0
0 1 2345 6 78
15 16
23 24 31
SI
52
ADDR ADDR ADDR
MSB
MSB
SO
HIGH IMPEDANCE
1295 32KBklEr.0
FIGURE 13: 32-KByte Block-Erase Sequence
CE#
MODE 3
SCK MODE 0
0 1 2345 6 78
15 16
23 24 31
SI
D8
ADDR ADDR ADDR
MSB
MSB
SO
HIGH IMPEDANCE
1295 63KBlkEr.0
FIGURE 14: 64-KByte Block-Erase Sequence
©2009 Silicon Storage Technology, Inc.
16
S71295-05-000
10/09
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