TB2110FN
○ Unlock detection bit
This bit is used to detect an unlock condition of the PLL circuit. When not locked (i.e., the reference frequency
and the programmable counter’s divided output are not locked in phase), the phase comparator outputs a pulse
to the unlock F / F synchronously with the period of the reference frequency. The unlock F / F is set by this pulse.
The unlock F / F is reset each time the reset bit of register 2 (unlock reset bit) is set to 1.
After the unlock F / F is reset in this way, you can access the unlock detection bit to see if the PLL circuit is in
lock condition. Because the pulse is input synchronously with the period of the reference frequency, you must
wait for a duration greater than the period of the reference frequency after resetting the unlock F / F before you
can access the unlock detection bit (unlock).
If this duration is short, you cannot detect the correct lock condition.
To solve this problem, the device has a lock enable F / F. This F / F is reset each time the unlock reset bit is set
to 1, and lock enable bit is set to 1 with the unlock detection timing. This means that you can detect the correct
unlock condition when the lock enable bit (enable) is 1.
Enable
0
1
Unlock
*
0
1
State
—
Lock
Unlock
12
2002-10-30