87C196LB View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

87C196LB

CHMOS 16-BIT MICROCONTROLLER

Intel 

AUTOMOTIVE

Name

T2CLK

T2DIR

TXJ1850

TXD

VCC

VPP

VREF

VSS, VSS1

®

Type

I

I

O

O

PWR

PWR

PWR

GND

Table 4. Signal Descriptions (Continued)

Description

Timer 2 External Clock

External clock for timer 2. Timer 2 increments (or decrements) on both rising

and falling edges of T2CLK. It is also used in conjunction with T2DIR for

quadrature counting mode.

T2CLK shares a package pin with P1.0 and EPA0.

Timer 2 External Direction

External direction (up/down) for timer 2. Timer 2 increments when T2DIR is

high and decrements when it is low. It is also used in conjunction with T2CLK

for quadrature counting mode.

T2DIR shares a package pin with P1.2 and EPA2.

Transmit

This signal carries messages from the integrated J1850 module to an off-chip

J1850 transceiver. TXJ1850 must not be driven high during reset and should

only be used as an output.

TXJ1850 shares a package pin with P2.6, ONCE#, and CPVER.

Transmit Serial Data

In serial I/O modes 1, 2, and 3, TXD transmits serial port output data. In mode

0, it is the serial clock output.

TXD shares a package pin with P2.0 and PVER.

Digital Supply Voltage

Connect each VCC pin to the digital supply voltage.

Programming Voltage

VPP causes the device to exit powerdown mode when it is driven low for at least

50 ns. Use this method to exit powerdown only when using an external clock

source because it enables the internal phase clocks, but not the internal

oscillator.

If you do not plan to use the powerdown feature, connect VPP to VCC.

Reference Voltage for the A/D Converter

This pin supplies operating voltage to the A/D converter.

Digital Circuit Ground (Core Ground, Port Ground)

These pins supply ground for the digital circuitry. Connect each VSS and VSS1

pin to ground through the lowest possible impedance path. VSS pins are con-

nected to the core ground region of the microcontroller, while VSS1 pins are con-

nected to the port ground region. (ANGND is connected to the analog ground

region.) Separating the ground regions provides noise isolation.

12

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