®
Name
WR#
WRL#
XTAL1
XTAL2
AUTOMOTIVE
Type
O
O
I
O
Table 4. Signal Descriptions (Continued)
Description
Write†
This active-low output indicates that an external write is occurring. This signal is
asserted only during external memory writes.
Forcing WR# high while RESET# is low, causes the device to enter PLL-bypass
mode. When the device is in PLL-bypass mode, the internal phase clocks
operate at one-half the frequency of the frequency on XTAL1.
WR# shares a package pin with P5.2, WRL#, and PLLEN.
† The chip configuration register 0 (CCR0) determines whether this pin
functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects
WRL#.
Write Low†
During 16-bit bus cycles, this active-low output signal is asserted for low-byte
writes and word writes to external memory. During 8-bit bus cycles, WRL# is
asserted for all write operations.
WRL# shares package pin with P5.2, WR#, and PLLEN.
† The chip configuration register 0 (CCR0) determines whether this pin
functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects
WRL#.
Input Crystal/Resonator or External Clock Input
Input to the on-chip oscillator and the internal clock generators. The internal
clock generators provide the peripheral clocks, CPU clock, and CLKOUT
signal. When using an external clock source instead of the on-chip oscillator,
connect the clock input to XTAL1. The external clock signal must meet the VIH
specification for XTAL1.
Inverted Output for the Crystal/Resonator
Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design
uses an external clock source instead of the on-chip oscillator.
PRODUCT PREVIEW
13