MSM82C55A-2GS View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
Manufacturer
MSM82C55A-2GS Datasheet PDF : 26 Pages
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¡ Semiconductor
MSM82C55A-2RS/GS/VJS
Type
Control Word
D7 D6 D5 D4 D3 D2 D1 D0
1 10000000
2 10000001
3 10000010
4 10000011
5 10001000
6 10001001
7 10001010
8 10001011
9 10010000
10 1 0 0 1 0 0 0 1
11 1 0 0 1 0 0 1 0
12 1 0 0 1 0 0 1 1
13 1 0 0 1 1 0 0 0
14 1 0 0 1 1 0 0 1
15 1 0 0 1 1 0 1 0
16 1 0 0 1 1 0 1 1
Port A
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Group A
High Order 4 Bits
of Port C
Output
Output
Output
Output
Input
Input
Input
Input
Output
Output
Output
Output
Input
Input
Input
Input
Notes: When used in mode 0 for both groups A and B
Port B
Output
Output
Input
Input
Output
Output
Input
Input
Output
Output
Input
Input
Output
Output
Input
Input
Group B
Low Order 4 Bits
of Port C
Output
Input
Output
Input
Output
Input
Ouput
Input
Output
Input
Output
Input
Output
Input
Output
Input
2. Mode 1 (Strobe input/output operation)
In mode 1, the strobe, interrupt and other control signals are used when input/output
operations are made from a specified port. This mode is available for both groups A and
B. In group A at this time, port A is used as the data line and port C as the control signal.
Following is a description of the input operation in mode 1.
STB (Strobe input)
When this signal is low level, the data output from terminal to port is fetched into the
internal latch of the port. This can be made independent from the CPU, and the data is not
output to the data bus until the RD signal arrives from the CPU.
IBF (Input buffer full flag output)
This is the response signal for the STB. This signal when turned to high level indicates that
data is fetched into the input latch. This signal turns to high level at the falling edge of STB
and to low level at the rising edge of RD.
INTR (Interrupt request output)
This is the interrupt request signal for the CPU of the data fetched into the input latch. It
is indicated by high level only when the internal INTE flip-flop is set. This signal turns to
high level at the rising edge of the STB (IBF = 1 at this time) and low level at the falling edge
of the RD when the INTE is set.
INTE A of group A is set when the bit for PC4 is set, while INTE B of group B is set when the
bit for PC2 is set.
Following is a description of the output operation of mode 1.
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