MSM82C55A-2GS View Datasheet(PDF) - Oki Electric Industry
Part Name
Description
Manufacturer
MSM82C55A-2GS Datasheet PDF : 26 Pages
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¡ Semiconductor
MSM82C55A-2RS/GS/VJS
OBF (Output buffer full flag output)
This signal when turned to low level indicates that data is written to the specified port upon
receipt of the WR signal from the CPU. This signal turns to low level at the rising edge of
the WR and high level at the falling edge of the ACK.
ACK (Acknowledge input)
This signal when turned to low level indicates that the terminal has received data.
INTR (Interrupt request output)
This is the signal used to interrupt the CPU when a terminal receives data from the CPU via
the MSM82C55A-5. It indicates the occurrence of the interrupt in high level only when the
internal INTE flip-flop is set. This signal turns to high level at the rising edge of the ACK
(OBF = 1 at this time) and low level at the falling edge of WR when the INTE B is set.
INTE A of group A is set when the bit for PC6 is set, while INTE B of group B is set when the
bit for PC2 is set.
Mode 1 Input
(Group A)
8
PA7
INTEA
PA0
(Group B)
8
PB7
INTEB
PB0
PC4
STBA
PC2
STBB
PC5
IBFA
PC1
IBFB
RD
RD
PC3
INTRA
PC0
INTRB
Note: Although belonging to group B, PC3 operates as the control signal of
group A functionally.
Mode 1 Output
(Group A)
8
PA7
INTEA
PA0
PC7
OBFA
PC6
ACKA
WR
WR
PC3
INTRA
(Group B)
PB7
INTEB
PB0
PC1
PC2
8
OBFB
ACKB
PC0
INTRB
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