TX4939 View Datasheet(PDF) - Toshiba
Part Name
Description
Manufacturer
TX4939 Datasheet PDF : 756 Pages
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Index
Toshiba RISC Processor
TX4939
24.3. Functional Description....................................................................................................................................... 24-2
24.3.1. CODEC Connection ................................................................................................................................... 24-3
24.3.2. Usage Flow ................................................................................................................................................ 24-5
24.3.3. AC-link Start Up.......................................................................................................................................... 24-7
24.3.4. CODEC Register Access ........................................................................................................................... 24-8
24.3.5. Sample-data Transmission and Reception................................................................................................. 24-9
24.3.6. DMA Channel Mapping ............................................................................................................................ 24-10
24.3.7. GPIO Operation ....................................................................................................................................... 24-14
24.3.8. Interrupt.................................................................................................................................................... 24-15
24.3.9. AC-link Low-power Mode ......................................................................................................................... 24-15
24.4. Registers......................................................................................................................................................... 24-16
24.4.1. ACLC Control Enable Register 0xF700............................................................................................. 24-17
24.4.2. ACLC Control Disable Register 0xF704............................................................................................ 24-21
24.4.3. ACLC CODEC Register Access Register 0xF708............................................................................... 24-24
24.4.4. ACLC Interrupt Status Register 0xF710 ............................................................................................ 24-25
24.4.5. ACLC Interrupt Masked Status Register 0xF714 ................................................................................ 24-27
24.4.6. ACLC Interrupt Enable Register 0xF718........................................................................................... 24-27
24.4.7. ACLC Interrupt Disable Register 0xF71C ......................................................................................... 24-27
24.4.8. ACLC Semaphore Register 0xF720.................................................................................................. 24-28
24.4.9. ACLC GPI Data Register 0xF740..................................................................................................... 24-29
24.4.10. ACLC GPO Data Register 0xF744.................................................................................................. 24-30
24.4.11. ACLC Slot Enable Register 0xF748 ................................................................................................ 24-31
24.4.12. ACLC Slot Disable Register 0xF74C............................................................................................... 24-33
24.4.13. ACLC FIFO Status Register 0xF750 ............................................................................................... 24-35
24.4.14. ACLC DMA Request Status Register 0xF780 .................................................................................. 24-37
24.4.15. ACLC DMA Channel Selection Register 0xF784 .............................................................................. 24-38
24.4.16. ACLC Audio PCM Output Data Register 0xF7A0 ACLC Surround Data Register 0xF7A4............ 24-39
24.4.17. ACLC Center Data Register 0xF7A4 ACLC LFE Data Register
0xF7AC ACLC Modem Output Data Register 0xF7B8 ........................ 24-40
24.4.18. ACLC Audio PCM Input Data Register 0xF7B0 ................................................................................ 24-41
24.4.19. ACLC Modem Input Data Register 0xF7BC..................................................................................... 24-42
24.4.20. ACLC Revision ID Register 0xF7FC ............................................................................................... 24-43
CHAPTER 25. ON-CHIP SRAM .................................................................................................................................... 25-1
25.1. Characteristics .................................................................................................................................................. 25-1
25.2. Block diagram ................................................................................................................................................... 25-1
25.3. Detailed explanation.......................................................................................................................................... 25-2
25.3.1. Base address ............................................................................................................................................. 25-2
25.3.2. Access cycle count..................................................................................................................................... 25-2
25.4. Register............................................................................................................................................................. 25-3
25.4.1. On-chip SRAM Control Register
0x6000........................................................................................... 25-3
CHAPTER 26. CRYPT ENGINE .................................................................................................................................... 26-1
26.1. Features............................................................................................................................................................ 26-1
26.1.1. CIPHER Engine ......................................................................................................................................... 26-1
26.1.2. Random Number Generator (RNG) ........................................................................................................... 26-1
26.2. Operational Overview of the CIPHER Engine ................................................................................................... 26-2
26.2.1. Ex-OR Function ......................................................................................................................................... 26-2
26.2.2. CIPHER DMA Controller ............................................................................................................................ 26-3
26.3. Operation Modes of the CIPHER Engine ........................................................................................................ 26-10
26.3.1. CBC Mode ............................................................................................................................................... 26-10
26.4. CIPHER Descriptors ....................................................................................................................................... 26-10
26.5. Programming Examples of the CIPHER Descriptors ...................................................................................... 26-13
26.5.1. Example 1 ................................................................................................................................................ 26-13
26.5.2. Example 2 ................................................................................................................................................ 26-13
26.5.3. Example 3 ................................................................................................................................................ 26-14
26.6. Random Number Generator (RNG) Engine .................................................................................................... 26-15
26.6.1. RNG Registers ......................................................................................................................................... 26-15
CHAPTER 27. EJTAG INTERFACE.............................................................................................................................. 27-1
27.1. Extended EJTAG Interface................................................................................................................................ 27-1
27.2. JTAG Boundary Scan Test ............................................................................................................................... 27-2
27.2.1. JTAG Controller and Register .................................................................................................................... 27-2
27.2.2. Instruction Register .................................................................................................................................... 27-3
27.2.3. Boundary Scan Register ............................................................................................................................ 27-4
27.2.4. Device ID Register ..................................................................................................................................... 27-4
Rev. 3.3 May 18, 2007
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