TX4939 View Datasheet(PDF) - Toshiba
Part Name
Description
Manufacturer
TX4939 Datasheet PDF : 756 Pages
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Toshiba RISC Processor
Index
TX4939
Figure 16-6 Initiator Access Memory Window..................................................................................................... 16-10
Figure 16-7 Address Conversion for Initiator (GBus -> PCI Bus Address Conversion)........................................16-11
Figure 16-8 Target Access Memory Window ...................................................................................................... 16-12
Figure 16-9 Address Conversion for Target (PCI Bus (PCI Bus → G-Bus Address Conversion) ....................... 16-13
Figure 16-10 Endian Switching........................................................................................................................... 16-14
Figure 16-11 Transition of the Power Management States ................................................................................. 16-15
Figure 16-12 PCI Req/Gnt connections in Int/Ext Arbiter Mode.......................................................................... 16-21
Figure 16-13 PCI Bus Arbitration Priority............................................................................................................ 16-22
Figure 16-14 ID Registers .................................................................................................................................. 16-27
Figure 16-15 PCI Status, Command Register..................................................................................................... 16-28
Figure 16-16 Class Code, Revision ID Register ................................................................................................. 16-30
Figure 16-17 PCI Configuration 1 Register......................................................................................................... 16-31
Figure 16-18 P2G Memory Space (m) PCI Lower Base Address Register (m=0,1,2)......................................... 16-32
Figure 16-19 P2G Memory Space (m) Configuration (m=0,1,2) ......................................................................... 16-33
Figure 16-20 P2G I/O Space PCI Base Address Register .................................................................................. 16-34
Figure 16-21 Subsystem ID Register.................................................................................................................. 16-35
Figure 16-22 Capabilities Pointer Register ......................................................................................................... 16-35
Figure 16-23 PCI Configuration 2 Register......................................................................................................... 16-36
Figure 16-24 G2P Timeout Count Register......................................................................................................... 16-37
Figure 16-25 G2P Status Register ...................................................................................................................... 16-37
Figure 16-26 G2P Interrupt Mask Register ......................................................................................................... 16-38
Figure 16-27 Satellite Mode PCI Status Register ............................................................................................... 16-39
Figure 16-28 PCI Status Interrupt Mask Register ............................................................................................... 16-40
Figure 16-29 P2G Configuration Register .......................................................................................................... 16-41
Figure 16-30 P2G Status Register...................................................................................................................... 16-42
Figure 16-31 P2G Interrupt Mask Register ......................................................................................................... 16-43
Figure 16-32 P2G Current Command Register .................................................................................................. 16-43
Figure 16-33 PCI Bus Arbiter Request Port Register.......................................................................................... 16-44
Figure 16-34 PCI Bus Arbiter Configuration Register ......................................................................................... 16-46
Figure 16-35 PCI Bus Arbiter Status Register..................................................................................................... 16-47
Figure 16-36 PCI Bus Arbiter Interrupt Mask Register........................................................................................ 16-47
Figure 16-37 PCI Bus Arbiter Broken Master Register ....................................................................................... 16-48
Figure 16-38 PCI Bus Arbiter Current Request Register .................................................................................... 16-49
Figure 16-39 PCI Bus Arbiter Current Grant Register......................................................................................... 16-49
Figure 16-40 PCI Bus Arbiter Current State Registe........................................................................................... 16-50
Figure 16-41 G2P Memory Space 0 G-Bus Base Address Register ................................................................... 16-51
Figure 16-42 G2P Memory Space 1 G-Bus Base Address Register ................................................................... 16-52
Figure 16-43 G2P Memory Space 2 G-Bus Base Address Register ................................................................... 16-53
Figure 16-44 G2P I/O Space G-Bus Address Register ....................................................................................... 16-54
Figure 16-45 G2P Memory Space 0 Address Mask Register.............................................................................. 16-55
Figure 16-46 G2P Memory Space 1 Address Mask Register.............................................................................. 16-55
Figure 16-47 G2P Memory Space 2 Address Mask Register.............................................................................. 16-56
Figure 16-48 G2P I/O Space Address Mask Register......................................................................................... 16-56
Figure 16-49 G2P Memory Space 0 G-Bus Base Address Register ................................................................... 16-57
Figure 16-50 G2P Memory Space 1 G-Bus Base Address Register ................................................................... 16-58
Figure 16-51 G2P Memory Space 2 G-Bus Base Address Register ................................................................... 16-59
Figure 16-52 G2P I/O Space G-Bus Address Register ....................................................................................... 16-60
Figure 16-53 PCI Controller Configuration Register ........................................................................................... 16-61
Figure 16-54 PCI Controller Status Register....................................................................................................... 16-64
Figure 16-55 PCI Controller Interrupt Mask Register.......................................................................................... 16-66
Figure 16-56 P2G Memory Space 0 G-Bus Base Address Register................................................................... 16-67
Figure 16-57 P2G Memory Space 1 G-Bus Base Address Register................................................................... 16-68
Figure 16-58 P2G Memory Space 2 G-Bus Base Address Register................................................................... 16-69
Figure 16-59 P2G I/O Space G-Bus Base Address Register .............................................................................. 16-70
Figure 16-60 G2P Configuration Address Register............................................................................................. 16-71
Figure 16-61 G2P Configuration Data Register .................................................................................................. 16-72
Figure 16-62 G2P Interrupt Acknowledge Data Register .................................................................................... 16-73
Figure 16-63 G2P Special Cycle Data Register.................................................................................................. 16-73
Figure 16-64 ID Register .................................................................................................................................... 16-74
Figure 16-65 Class Code/Revision ID Register .................................................................................................. 16-74
Figure 16-66 Sub System ID Register ................................................................................................................ 16-75
Figure 16-67 PCI Configuration Register 2......................................................................................................... 16-75
Figure 16-68 PDMAC Chain Address Register................................................................................................... 16-76
Figure 16-69 G-Bus Address Register................................................................................................................ 16-77
Figure 16-70 PCI Bus Address Register ............................................................................................................. 16-78
Figure 16-71 Count Register .............................................................................................................................. 16-79
Rev. 3.3 May 18, 2007
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