TX4939 View Datasheet(PDF) - Toshiba
Part Name
Description
Manufacturer
TX4939 Datasheet PDF : 756 Pages
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Toshiba RISC Processor
Index
TX4939
Figure 12-6 Serial transmission format with 188 Byte packets ............................................................................. 12-5
Figure 12-7 Serial transmission format with 204 Byte packets ............................................................................. 12-5
Figure 12-8 Serial transmission format with RS-coded packets (204 Bytes) ........................................................ 12-5
Figure 12-9 Transmit Window 2 data to video port ............................................................................................... 12-7
Figure 13-1 Connecting Timer Module Inside the TX4939.................................................................................... 13-2
Figure 13-2 Timer Internal Block Diagram ............................................................................................................ 13-3
Figure 13-3 Operation Example of Interval Timer (Using Internal Clock).............................................................. 13-6
Figure 13-4 Operation Example of the Interval Timer (External Input Clock: Falling Edge Operation) ................. 13-6
Figure 13-5 Operation Example of the Pulse Generator Mode............................................................................. 13-7
Figure 13-6 Operation Example of the Watchdog Timer Mode............................................................................. 13-9
Figure 13-7 Timer Control Register .....................................................................................................................13-11
Figure 13-8 Timer Interrupt Status Register........................................................................................................ 13-12
Figure 13-9 Compare Register A ........................................................................................................................ 13-14
Figure 13-10 Compare Register B...................................................................................................................... 13-15
Figure 13-11 Interval Timer Mode Register......................................................................................................... 13-16
Figure 13-12 Divide Register .............................................................................................................................. 13-17
Figure 13-13 Pulse Generator Mode Register .................................................................................................... 13-18
Figure 13-14 Watchdog Timer Mode Register .................................................................................................... 13-19
Figure 13-15 Timer Read Register 0 .................................................................................................................. 13-20
Figure 14-1 DMA0 Controller Block Diagram........................................................................................................ 14-2
Figure 14-2 DMA1 Controller Block Diagram........................................................................................................ 14-3
Figure 14-3 Non-aligned Single Address Burst Transfer....................................................................................... 14-9
Figure 14-4 Dual Address Burst Transfer (DMCCRn.USEXFSZ = 1) ..................................................................14-11
Figure 14-5 (b) Dual Address Burst Transfer (DMCCRn.USEXFSZ = 0) ............................................................ 14-13
Figure 14-6 DMA Command Descriptor Chain ................................................................................................... 14-15
Figure 14-7 DMA Controller Interrupt Signal....................................................................................................... 14-17
Figure 14-8 DMA Channel Arbitration ................................................................................................................. 14-18
Figure 14-9 DMA Master Control Register.......................................................................................................... 14-22
Figure 14-10 DMA Channel Control Register ..................................................................................................... 14-24
Figure 14-11 DMA Channel Status Register ....................................................................................................... 14-28
Figure 14-12 DMA Source Address Register ...................................................................................................... 14-30
Figure 14-13 DMA Destination Address Register ............................................................................................... 14-31
Figure 14-14 DMA Chain Address Register ........................................................................................................ 14-32
Figure 14-15 DMA Source Address Increment Register ..................................................................................... 14-33
Figure 14-16 DMA Destination Address Increment Register .............................................................................. 14-34
Figure 14-17 DMA Count Register...................................................................................................................... 14-35
Figure 14-18 DMA Memory Fill Data Register .................................................................................................... 14-36
Figure 14-19 Dual Address Transfer from External I/O Device to SRAM
(4-word Burst Transfer to 16-bit Bus SRAM) ................................................................................. 14-37
Figure 14-20 Dual Address Transfer from Memory to External I/O Device
(4-word Burst Transfer from 16-bit Bus SRAM) ............................................................................. 14-38
Figure 14-21 Dual Address Transfer from External I/O Device to SRAM
(2-word Burst Transfer to 16-bit SRAM) ........................................................................................ 14-39
Figure 14-22 Dual Address Transfer from External I/O Device
(Non-Burst) to Memory (2-word Burst Transfer to 16-bit SRAM: Set DMCCRn.SBINH to “1”) ...... 14-40
Figure 14-23 Dual Address Transfer from Memory to External I/O Device
(2-word Burst Transfer from 16-bit SRAM: Set DMCCRn.DBINH to “1”) ....................................... 14-41
Figure 15-1 Read Command ................................................................................................................................ 15-4
Figure 15-2 Burst Read of 4 ................................................................................................................................. 15-5
Figure 15-3 Write Command ................................................................................................................................ 15-6
Figure 15-4 Example of Burst Write 4................................................................................................................... 15-7
Figure 15-5 Precharge Command ........................................................................................................................ 15-8
Figure 15-6 Power-Down Command .................................................................................................................... 15-9
Figure 15-7 Example of DDR Memory Split-Mapping ..........................................................................................15-11
Figure 15-8 DDR Mapping Window Control ....................................................................................................... 15-13
Figure 15-9 DDR Mapping Window Control ....................................................................................................... 15-14
Figure 15-10 dqs Read Timing ........................................................................................................................... 15-30
Figure 15-11 dqs Arrival Window ........................................................................................................................ 15-31
Figure 15-12 dqs Write Timing............................................................................................................................ 15-32
Figure 15-13 Controller Memory Map: Maximum .............................................................................................. 15-33
Figure 15-14 Alternate Memory Map .................................................................................................................. 15-33
Figure 16-1 PCI Controller Block Diagram ........................................................................................................... 16-3
Figure 16-2 PCI BOOT default mapping............................................................................................................... 16-5
Figure 16-3 Block Diagram of Sample PCI Adapter.............................................................................................. 16-6
Figure 16-4 Register Map (Host Mode) ................................................................................................................ 16-7
Figure 16-5 Register Map (Satellite Mode) ........................................................................................................... 16-7
Rev. 3.3 May 18, 2007
xiv
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