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UPD62A View Datasheet(PDF) - NEC => Renesas Technology

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UPD62A Datasheet PDF : 62 Pages
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µPD62A
3.1 KI/O Port (P0)
The KI/O port is an 8-bit input/output port for key scan output.
Input/output mode is set by bit 1 of the P4 register.
If a read instruction is executed, the pin state can be read in input mode, whereas the output latch contents can
be read in output mode.
If the write instruction is executed, data can be written to the output latch regardless of input or output mode.
When reset, the port is placed in output mode; and the value of the output latch (P0) becomes 1111 1111B.
The KI/O port includes a pull-down resistor, allowing pull-down in input mode only.
Caution If a key is double-pressed, a high-level output and a low-level output may coincide at the
KI/O port. To avoid this, the low-level output current of the KI/O port is held low. Therefore, be
careful when using the KI/O port for purposes other than key scan output.
The KI/O port is so designed that, even when connected directly to VDD, within the normal supply
voltage range (VDD = 2.0 to 3.6 V), no problem may occur.
Bit
Name
Table 3-2. KI/O Port (P0)
b7
KI/O7
b6
KI/O6
b5
KI/O5
b4
KI/O4
b3
KI/O3
b2
KI/O2
b1
KI/O1
b0
KI/O0
b0 to b7: Read:
Write:
In input mode, the KI/O pin’s state is read.
In output mode, the KI/O pin’s output latch contents are read.
Data is written to the KI/O pin’s output latch regardless of input or output mode.
Data Sheet U14474EJ1V0DS00
15

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