UPD77115 View Datasheet(PDF) - NEC => Renesas Technology

Part Name

Description

Manufacturer

UPD77115

16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR

NEC => Renesas Technology 

µPD77115, 77115A

2.3 Data Memory Unit

The data memory unit consists of two banks of data memory and two data addressing units.

2.3.1 Data memory

The DSP have two banks of data memory (X data memory and Y data memory). A 64-word peripheral area is

assigned in the data memory space.

The µPD77115 has 16K words × 2 banks data RAM.

2.3.2 Data addressing unit

An independent data addressing unit is provided for each of the X data memory and Y data memory spaces.

Each data addressing unit has four data pointers (DPn), four index registers (DNn), one modulo register (DMX or

DMY), and an address ALU.

2.4 Peripheral Unit

A serial interface, host interface, general-purpose I/O port, and wait cycle register are provided. All these internal

peripherals are mapped to the X data memory and Y data memory spaces, and are accessed from program as

memory-mapped I/Os.

2.4.1 Audio Serial interface (ASIO)

One serial interface is provided. This serial interface has two mode which are the audio serial and the standard

serial. The standard serial is compatible other µPD77111 family DSP.

The audio serial interfaces have the following features:

• Mode : Master mode or Slave mode

Master mode : MCLK (input), BCLK (output), LRCLK (output), support 256 fs, 384 fs and 512 fs

Slave mode : MCLK (unused), BCLK (input), LRCLK (input)

• Frame format : 32 or 64 bits audio format (LRCLK format), MSB first input/output.

• Handshake : Handshaking with the external devices is implemented with a dedicated frame signal (LRCLK).

Handshaking with the internal units, polling, wait, or interrupt are used.

The standard serial interfaces have the following features:

• Serial clock : Supplied from external source to each interface. The same clock is used for input and output

on the interface.

• Frame length : 8 or 16 bits, and MSB or LSB first selectable for each input or output

• Handshake : Handshaking with external devices is implemented with a dedicated status signal. With the

internal units, polling, wait, or interrupt are used.

2.4.2 Host interface (HIO)

This is an 16-bit parallel port that inputs data from or outputs data to an external host CPU or DMA controller. In

the DSP, a 16-bit register is mapped to memory for input data, output data, and status. Handshaking with an external

device is implemented by using a dedicated status signal or a dedicated status register. Handshaking with internal

units is achieved by means of polling, wait, or interrupts.

Data Sheet U14867EJ5V0DS

17

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