UPD77115 View Datasheet(PDF) - NEC => Renesas Technology

Part Name

Description

Manufacturer

UPD77115

16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR

NEC => Renesas Technology 

µPD77115, 77115A

2.4.3 General-purpose I/O port (PIO)

This is a 8-bit I/O port that can be set in the input or output mode in 1-bit units.

2.4.4 SD card interface (SDCIF)

This interface is for access SD card. It supports the DMA transfer for input data to internal data RAM. The SD card

is accessed by using a dedicated routine of system ROM.

2.4.5 Timer

This is 16-bit timer unit. The count source can be selected from system clock, SD card clock, serial clock and INT4

input. Timer unit generates interrupt for interface internal units.

3. RESET FUNCTION

When a low level of a specified width is input to the RESET pin, the device is initialized.

3.1 Hardware Reset

If the RESET pin is asserted active (low level) for a specified period, the internal circuitry of the DSP is initialized. If

the RESET pin is then deasserted inactive (high level), boot processing of the instruction RAM is performed according

to the status of the port pins (P0 and P1). After boot processing, processing is executed starting from the instruction

at address 0x200 of instruction memory (reset entry).

No power-ON reset function is available.

3.2 Initializing PLL

Initializing the PLL starts during boot up program at reset. The pins (PLL0 to PLL3) that specify the PLL multiple

rate must be kept stable for the duration of 3 clocks before and for the duration of 50 clocks after reset has been

cleared (the clock is input from CLKIN). It takes the PLL 100 µs to be locked. Until the PLL is lacked, the DSP internal

is operated by the CLKIN clock.

To use the PLL clock as an internal operating clock, set the clock control register (internal peripheral) by user

program.

4. FUNCTIONS OF BOOT-UP ROM

To rewrite the contents of the instruction memory on power application or from program, boot up the instruction

RAM by using the internal boot-up ROM.

The µPD77115 has a function to verify the contents of the internal instruction RAM.

4.1 Boot at Reset

After hardware reset has been cleared, the boot program first reads the general-purpose I/O ports P0 and P1 and,

depending on their bit pattern, determines the boot mode (host boot or non boot). After boot processing, processing is

executed starting from the instruction at address 0x200 (reset entry) of the instruction memory.

The pins (P0 and P1) that specify the boot mode must be kept stable for the duration of 3 clocks before and for the

duration of 12 clocks after reset has been cleared (the clock is input from CLKIN).

18

Data Sheet U14867EJ5V0DS

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