Z89C00 Datasheet PDF

Z89C00 View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z89C00

16-BIT DIGITAL SIGNAL PROCESSOR

Zilog

Z89C00 Datasheet PDF : 28 Pages

First Prev 11 12 13 14 15 16 17 18 19 20 Next Last

ZILOG

Inst. Description Synopsis

LD Load destination LD<dest>,<src>

with source

PRELIMINARY

Z89C00

16-BIT DIGITAL SIGNAL PROCESSOR

Operands

A,<hwregs>

A,<dregs>

A,<pregs>

A,<regind>

A,<memind>

A,<direct>

<direct>,A

Words Cycles Examples

1 1 LD A,X

1 1 LD A,D0:0

1 1 LD A,P0:1

1 1 LD A,@P1:1

1 3 LD A,@D0:0

1 1 LD A,124

1 1 LD 124,A

1 1 LD D0:0,EXT7

1 1 LD P1:1,#%FA

1 1 LD P1:1,EXT1

1 1 LD@P1:1,#1234

1 1 LD @P1:1+,X

1 1 LD Y,P0:0

1 1 LD SR,D0:0

2 2 LD PC,#%1234

1 3 LD X,@A

1 3 LD Y,@D0:0

1 1 LD A,@P0:0–LOOP

1 1 LD X,EXT6

Note: If X or Y register is the destination, an automatic multiply

operation is performed.

Note: The P register is Read Only and cannot be destination.

Note: LD EXTN, EXTN is not allowed.

Note: LD A, @A is not allowed.

MLD Multiply

MLD<src1>,<src2>[,<bank switch>]

<hwregs>,<regind>,<bank switch> 1

<regind>,<regind>,<bank switch> 1

1 MLD A,@P0:0+LOOP

1 MLD A,@P1:0,OFF

1 MLD @P1:1,@P2:0

1 MLD @P0:1,@P1:0,ON

Note: If src1 is <regind> it must be a bank 1 register.

Src2’s <regind must be a bank 0 register.

Note: <hwregs> for src1 cannot be X.

Note: For the operands <hwregs>, <regind> the <band switch> defaults to OFF.

For the operands <regind>, the <bank switch> defaults to ON.

MPYA Multiply and add

MPYA <src1>,<src2>[,<bank switch>]

<hwregs>,<regind>,<bank switch> 1

<regind>,<regind>,<bank switch> 1

1 MPYA A,@P0:0

1 MPYA A,@P1:0,OFF

1 MPYA @P1:1,@P2:0

1 MPYA@P0:1,@P1:0,ON

Note: If src1 is <regind> it must be a bank 1 register.

Src2’s <regind> must be a bank 0 register.

Note: <hwregs> for src1 cannot be X or A.

Note: For the operands <hwregs>, <regind> the <bank switch> defaults to

OFF. For the operands <regind>, the <bank switch> defaults to ON.

DC 4083-00

Share Link: