Z89C00 View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z89C00

16-BIT DIGITAL SIGNAL PROCESSOR

Zilog 

ZILOG

PRELIMINARY

INSTRUCTION DESCRIPTIONS (Continued)

Z89C00

16-BIT DIGITAL SIGNAL PROCESSOR

Inst. Description

MPYS Multiply and

subtract

Synopsis

Operands

Words Cycles Examples

MPYS<src1>,<src2>[,<bank switch>]

<hwregs>,<regind>

1

<hwregs>,<regind>,<bank switch> 1

<regind>,<regind>

1

<regind>,<regind>,<bank switch> 1

1 MPYS A,@P0:0

1 MPYS A,@P1:0,OFF

1 MPYS @P1:1,@P2:0

1 MPYS @P0:1,@P1:0,ON

Note: If src1 is <regind> it must be a bank 1 register.

Src2’s <regind> must be a bank 0 register.

Note: <hwregs> for src1 cannot be X or A.

Note: For the operands <hwregs>, <regind> the <bank switch> defaults to OFF.

For the operands <regind>, <regind> the <bank switch> defaults to ON.

NEG Negate

NOP No operation

OR Bitwise OR

NEG <cc>,A

NOP

OR <dest>,<src>

POP Pop value

from stack

PUSH Push value

onto stack

POP <dest>

PUSH <src>

RET Return from subroutine RET

RL Rotate Left

RL <cc>,A

RR Rotate Right

RR <cc>,A

<cc>, A

A

None

A, <pregs>

A, <dregs>

A, <limm>

A, <memind>

A, <direct>

A, <regind>

A, <hwregs>

<pregs>

<dregs>

<regind>

<hwregs>

<pregs>

<dregs>

<regind>

<hwregs>

<limm>

<accind>

<memind>

None

<cc>,A

A

<cc>,A

A

1 1 NEG MI,A

1 1 NEG A

1 1 NOP

1 1 OR A,P0:1

1 1 OR A, D0:1

2 2 OR A,#%2C21

1 3 OR A,@@P2:1+

1 1 OR A, %2C

1 1 OR A,@P1:0–LOOP

1 1 OR A,EXT6

1 1 POP P0:0

1 1 POP D0:1

1 1 POP @P0:0

1 1 POP A

1 1 PUSH P0:0

1 1 PUSH D0:1

1 1 PUSH @P0:0

1 1 PUSH BUS

2 2 PUSH #12345

1 3 PUSH @A

1 3 PUSH @@P0:0

1 2 RET

1 1 RL NZ,A

1 1 RL A

1 1 RR C,A

1 1 RR A

18

DC 4083-00

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