Z89C00 View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z89C00

16-BIT DIGITAL SIGNAL PROCESSOR

Zilog 

ZILOG

PRELIMINARY

Inst. Description

SCF Set C flag

SIEF Set IE flag

SLL Shift left

logical

SOPF Set OP flag

SRA Shift right

arithmetic

SUB Subtract

Synopsis

SCF

SIEF

SLL

SOPF

SRA<cc>,A

SUB<dest>,<src>

XOR Bitwise exclusive OR XOR <dest>,<src>

Operands

None

None

[<cc>,]A

A

None

<cc>,A

A

A,<pregs>

A,<dregs>

A,<limm>

A, <memind>

A, <direct>

A, <regind>

A, <hwregs>

A, <pregs>

A, <dregs>

A, <limm>

A, <memind>

A, <direct>

A, <regind>

A, <hwregs>

Z89C00

16-BIT DIGITAL SIGNAL PROCESSOR

Words Cycles Examples

1 1 SCF

1 1 SIEF

1 1 SLL NZ,A

1 1 SLL A

1 1 SOPF

1 1 SRA NZ,A

1 1 SRA A

1 1 SUB A,P1:1

1 1 SUB A,D0:1

2 2 SUB A,#%2C2C

1 3 SUB A,@D0:1

1 1 SUB A,%15

1 1 SUB A,@P2:0-LOOP

1 1 SUB A,STACK

1 1 XOR A,P2:0

1 1 XOR A,D0:1

2 2 XOR A,#13933

1 3 XOR A,@@P2:1+

1 1 XOR A,%2F

1 1 XOR A,@P2:0

1 1 XOR A,BUS

Bank Switch Enumerations. The third (optional) operand

of the MLD, MPYA and MPYS instructions represents

whether a bank switch is set on or off. To more clearly

represent this, two keywords are used (ON and OFF)

which state the direction of the switch. These keywords are

referred to in the instruction descriptions through the

<bank switch> symbol.

DC 4083-00

19

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