SAK-XC2765X-104F80LAA View Datasheet(PDF) - Infineon Technologies

Part Name

Description

Manufacturer

SAK-XC2765X-104F80LAA

16/32-Bit Single-Chip Microcontroller with 32-Bit Performance XC2000 Family / Base Line

Infineon Technologies 

XC27x5X Derivatives

XC2000 Family / Base Line

Detailed Errata Description

device starts with a CAN bootstrap loader without limitation of the oscillator

settling time.

DPRAM_X.002 Undefined Data read from Dual-Port RAM (DPRAM)

Under special conditions, undefined data may be read from up to two word

locations L1, L2 in the DPRAM (address range F600H .. FDFFH).

The problem (affecting L1 and/or L2) is due to a redundancy circuit that may not

be properly disabled during the internal power-up reset sequence.

The problem may only occur when an operand that was written via port B is

(later) read via port A of the DPRAM. This is only the case when dual read

transfers are performed on both port A and B in parallel, which can only happen

in the two scenarios described below.

Note: Field experience has shown that the probability for this problem is

relatively low, as it further depends on several other conditions, e.g.:

- For an initial power-on reset without residual voltage, the problem is less

likely to occur at room temperature and above.

- The problem is more likely to occur when a residual voltage at VDDI1

was present at the last power-off/on cycle.

- If the problem does occur, then it is “latched” at power up. If it hasn’t

occurred in the current power cycle, then the problem only has the

possibility of occurring at the next power-off/on cycle.

- The addresses of L1 and L2 may vary from device to device and from one

power-off/on cycle to the next, but will not change for a given device until

the next power-off/on cycle; i.e. if L1 and L2 are not read via port A in one

of the critical scenarios described below, the problem has no effect on the

application.

Scenario 1 (Context Switch)

In this scenario, the problem may occur under the following sequence of

conditions (all conditions must be met):

1. L1 and/or L2 are located in the DPRAM in an area that is used to store the

context of a global register bank, and

Errata Sheet

23

V1.5, 2013-02

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