SAK-XC2765X-104F80LAA View Datasheet(PDF) - Infineon Technologies

Part Name

Description

Manufacturer

SAK-XC2765X-104F80LAA

16/32-Bit Single-Chip Microcontroller with 32-Bit Performance XC2000 Family / Base Line

Infineon Technologies 

XC27x5X Derivatives

XC2000 Family / Base Line

Detailed Errata Description

ESR_X.001 ESREXSTAT1 and ESREXSTAT2 Status Bits are Cleared by

Hardware

The status bits of register ESREXSTAT1 and ESREXSTAT2 are set as the trigger

signal was active. The status bits are not stored and are only set as long as the

external trigger inputs are active.

Workaround

None.

ESR_X.004 Wrong Value of SCU_RSTCONx Registers after ESRy Applica-

tion Reset

SCU_RSTCONx registers are reset only by Power-On, but they may be wrongly

affected after a second application reset requested by an ESRy pin. This may

lead to the SCU_RSTCONx register values being set to zero, which could

unexpectedly disable reset sources within the user application. The conditions

which lead to this behavior are:

1. First, an application reset by SW (software), CPU (Central Processing Unit),

MP (Memory), WDT (Watchdog Timer) or ESRy (External Service Request

y) occurs.

2. Following this, an application reset on an ESRy pin occurs.

3. If the above mentioned ESRy reset occurs during a critical time window of

the SSW (startup software), then it’s possible that the application will

operate with the wrong SCU_RSTCONx register value. The critical time

window occurs when the SSW is writing the SCU_RSTCONx registers, and

at the same time, the ESRy reset request is processed by the reset circuitry.

The width of this critical window fcritical window is less than 13 cycles.

Errata Sheet

29

V1.5, 2013-02

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