SAK-XC2765X-104F80LAA View Datasheet(PDF) - Infineon Technologies

Part Name

Description

Manufacturer

SAK-XC2765X-104F80LAA

16/32-Bit Single-Chip Microcontroller with 32-Bit Performance XC2000 Family / Base Line

Infineon Technologies 

XC27x5X Derivatives

XC2000 Family / Base Line

Detailed Errata Description

Application

Reset

Reset

by ESRy pin

SSW

Application Application

Software

Runs

tcritical window

Start of

SSW

Write

RSTCON

Start of

SSW

Figure 2 Critical application reset sequence

End of

SSW

Application

Runs

ESR_X.004 Fig. 1

Workaround

• Initialize SCU_RSTCONx registers by user software after any reset, or

• assure that a second application reset request with an ESR pin does not

occur during the critical time window.

GPT12E_X.002 Effects of GPT Module Microarchitecture

The present GPT module implementation provides some enhanced features

(e.g. block prescalers BPS1, BPS2) while still maintaining timing and functional

compatibility with the original implementation in the C166 Family of

microcontrollers.

Both the GPT1 and GPT2 blocks use a finite state machine to control the

actions within each block. Since multiple interactions are possible between the

timers (T2 .. T6) and register CAPREL, these elements are processed

sequentially within each block in different states. However, all actions are

normally completed within one basic clock cycle.

The GPT2 state machine has 4 states (2 states when BPS2 = 01B) and

processes T6 before T5. The GPT1 state machine has 8 states (4 states when

BPS1 = 01B) and processes the timers in the order T3 - T2 (all actions except

capture) - T4 - T2 (capture).

In the following, two effects of the internal module microarchitecture that may

require special consideration in an application are described in more detail.

Errata Sheet

30

V1.5, 2013-02

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