CXD1961Q View Datasheet(PDF) - Sony Semiconductor
Part Name
Description
Manufacturer
CXD1961Q Datasheet PDF : 15 Pages
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CXD1961Q
(2) Analog to Digital Converters
The Dual 6 bit A to D converters quantize the analog I/Q input data. The input range of the ADC's is
determined by external resistors. RT0 (RT1) is the top reference voltage, and RB0 (RB1) is the bottom
reference voltage. RT0 (RT1) and RB0 (RB1) are connected internally with a 320 Ω (Typical value) resistor.
In the example shown in the following figure, input range is approximately 1.1 V, and center voltage 1.65 V.
AVD (+3.3V)
330Ω
CXD1961Q
RT
Top reference level
330Ω
320Ω
Input range
RB
Bottom reference level
AVS (0V)
(3) AGC
Input signal level of the A to D Converter is estimated by calculating I2+Q2 in 16 bit precision, and the upper
8 bits of the estimated data are sent via the CPU I/F as ADC_IN [7:0]. CXD1961Q has two AGC modes that
can be selected by AGC_MOD. In AGC slave mode, ADC_IN[7:0] is checked and an appropriate gain level
AGC[7:0] is returned by the micro controller. This value is converted into 8 bit PWM format and output from
AGCPWM (Pin 68).
In AGC master mode, reference level AGC[7:0] is set via the CPU I/F and compared to ADC_IN[7:0]
internally. The updated gain level is then output at the AGCPWM pin. In normal operation, ADC_IN[7:0]
becomes almost equal to reference level. In AGC master mode, AGC control interval is set by TIMER[2:0].
In both modes, AGCPWM output should be low pass filtered, and if needed, the level should be converted
to satisfy the AGC gain control range. Depending on AGC_INV, the polarity can be inverted. (H:positive /
L:negative)
CPU Register
ADC_IN [7 : 0] →
AGC_MOD
→
Reference level
ADC_IN [7 : 0]
0F
3F
7F
FF
ADD 0h
AGC [7 : 0] →
ADD 7h
TIMER [2 : 0] →
Input signal level
to ADC input range ratio
0.25
0.5
0.7
1.0 or over range
ADD 4h
ADD 7h
AGC_INV
→ ADD 7h
Note)
ADC input range is subject to temperature and VDD level.
—11—
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