4282 Group
TIMING REQUIREMENT CONDITION AND SWITCHING CHARACTERISTICS
(Ta = 25 °C, VDD = 4.0 V, VPP = 12.5 V)
Symbol
Parameter
Limits
Min. Max. Unit
tCH Serial transfer width time
2.0
µs
tCR Read wait time after transfer
2.0
µs
tWR Read pulse width
500
ns
tRC Transfer wait time after read
2.0
µs
tCP Program wait time after transfer
2.0
µs
tWP Program pulse width
0.19 0.21 ms
tOWP Added program pulse width
0.19 5.25 ms
tC(CK) SCLK input cycle time
1.0
µs
tW(CKH) SCLK “H” pulse width
450
ns
tW(CKL) SCLK “L” pulse width
450
ns
tr(CK) SCLK rising time
40
ns
tf(CK) SCLK falling time
40
ns
td(C–Q) SDA output delay time
0 180 ns
th(C–Q) SDA output hold time
0
ns
th(C–E) SDA output hold time (only for 16th bit) 100
ns
tsu(D–C) SDA input set-up time
60
ns
th(C–D) SDA input hold time
180
ns
TIMING DIAGRAM
SCLK
SDA output
SDA input
tf(CK)
tW(CKL)
tC(CK)
tr(CK)
td(C-Q)
tW(CKH)
th(C-E)
th(C-Q)
tsu(D-C) th(C-D)
Measurement condition
Output timing voltage: VOL = 0.8 V, VOH = 2.0 V
Input timing voltage: VIL = 0.2 VDD, VIH = 0.8 VDD
Rev.1.33 Mar 18, 2004 page 65 of 67