AD9875-EB View Datasheet(PDF) - Analog Devices
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AD9875-EB Datasheet PDF : 24 Pages
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AD9875
AGC TIMING CONSIDERATIONS
When implementing the AGC timing loop it is important to
consider the delay and settling time of the Rx path in response
to a change in gain. Figure 4 shows the delay the receive signal
experiences through the blocks of the Rx path. Whether the gain
is programmed through the serial port or over the TX[5:0] pins,
the gain takes effect immediately with the delays shown below.
When gain changes do not involve the CPGA, the new gain will
be evident in samples after seven ADC clock cycles. When the
gain change does involve the CPGA, it takes an additional 45 ns
to 70 ns due to the propagation delays of the buffer, LPF and
PGA. Table III, in the Register Programming section, details the
PGA programming map.
GAIN
REGISTER
5ns
DECODE
LOGIC
DIGITAL
HPF
1 CLK
CYCLE
ADC
5 CLK
CYCLE
SHA
1/2 CLK
CYCLE
BUFFER
LPF
PGA
10ns 25ns OR 50ns 10ns
Figure 4. AGC Timing
Transmit Port Timing
The AD9875 transmit port consists of a 6-bit data bus Tx[5:0],
a clock and a Tx SYNC signal. Two consecutive nibbles of the
Tx data are multiplexed together to form a 10-bit data word.
The clock appearing on the CLK-A pin is a buffered version of
the internal Tx data sampling clock. Data from the Tx port is
read on the rising edge of this sampling clock. The Tx SYNC
signal is used to indicate to which word a nibble belongs. The
first nibble of every word is read while Tx SYNC is low, the
second nibble of that same word is read on the following Tx
SYNC high level. The timing is illustrated in the Figure 5.
CLK-A
Tx SYNC
tSU
tHD
Tx [5:0]
Tx0 LSB Tx1 MSB Tx1 LSB Tx2 MSB Tx2 LSB Tx3 MSB
Figure 5. Transmit Timing Diagram AD9875
The Tx port is highly configurable and offers the following
options:
Also, the Tx path can be used in a reduced resolution mode by
setting the Tx Port Multiplexer Bypass bit (Register 7, Bit 0). In
this mode the Tx data word becomes six bits and is read in a
single cycle. The clocking modes are the same as described
above, but the level of Tx SYNC is irrelevant.
If Tx SYNC is low for more than one clock cycle, the last trans-
mit data will read continuously until Tx SYNC is brought high
for the second nibble of a new transmit word. This feature can
be used to “flush” the interpolator filters with zeros.
PGA Gain Adjust Timing
In addition to the serial port, the Tx[5:1] pins can be used to
write to the Rx Path Gain Adjust bits (Register 6, Bits 4:0). This
provides a faster way to update the PGA gain. A high level on
the GAIN pin with Tx SYNC low programs the PGA setting on
the rising edge of CLK-A. A low level on the GAIN pin enables
data to be fed to the interpolator and DAC. The GAIN pin
must be held high, the Tx SYNC must be held low, and
the GAIN data must be stable for three clock cycles to
successfully update the PGA GAIN value.
It should be noted that Tx SYNC must be held low and Tx
GAIN must be held high to update the gain register. If Tx
GAIN and Tx SYNC are both high, no data is written to the
gain register of the Tx data path.
CLK-A
Tx SYNC
Tx [5:0]
GAIN
tSU
tHD
GAIN
Figure 6. GAIN Programming
Receive Port Timing
The AD9875 receives port consists of a six bit data bus Rx[5:0],
a clock and an Rx SYNC signal. Two consecutive nibbles of the
Rx data are multiplexed together to form a 10-bit data word.
The Rx data is valid on the rising edge of CLK-A when the
ADC Clock Source PLL-B/2 bit (Register 3, Bit 6) is set to 0.
The Rx SYNC signal is used to indicate to which word a nibble
belongs. The first nibble of every word is transmitted while Rx
SYNC is low, the second nibble of that same word is transmit-
ted on the following Rx SYNC high level. When Rx SYNC is
low, the sampled nibble is read as the most significant nibble.
When the Rx SYNC is high, the sampled nibble is read as the
least significant nibble. The timing is illustrated in Figure 7.
Negative edge sampling can be chosen by two different methods;
either by setting the Tx Port Negative Edge Sampling bit (Register 3,
Bit 7) or the Invert CLK-A bit (Register 8, Bit 6). The main differ-
ence between the two methods is that setting Register 3, Bit 7
inverts the internal sampling clock and will affect only the transmit
path, even if CLK–A is used to clock the Rx data. Inverting CLK-A
would affect both the Rx and Tx paths if they both use CLK-A.
The first nibble of each word can be read in as the least significant
nibble by setting the Tx LS Nibble First bit (Register 7, Bit 2).
For the AD9875, the most significant nibble defaults to six bits
and the least significant nibble defaults to form four bits. This
can be changed so that the least significant nibble and most
significant nibble have five bits each. This is done by setting the
Tx Port Width Five Bits bit (Register 7, Bit 1). In all cases, the
nibbles are justified toward Bit 5.
CLK-A (-B)
Rx SYNC
tHT
tVT
Rx [5:0]
Rx0 LSB Rx1 MSB Rx1 LSB Rx2 MSB Rx2 LSB Rx3 MSB
Figure 7. Receive Timing Diagram
The Rx port is highly configurable and offers the following
options:
Negative edge sampling can be chosen by setting the Invert
CLK-A bit (Register 8, Bit 6) or the Invert CLK-B bit (Register
8, Bit 7), depending on the clock selected as the ADC sampling
source. Inverting CLK-A would affect the Tx sampling edge as
well as the Rx sampling edge.
The first nibble of each word can be read in as the least signifi-
cant nibble by setting the Rx LS Nibble First bit (Register 8, Bit 2).
–18–
REV. 0
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