MSC8122 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MSC8122

Quad Digital Signal Processor

Freescale Semiconductor 

Hardware Design Considerations

Figure 34. For optimal noise filtering, place the circuit as close as possible to VCCSYN. The 0.01-µF capacitor should be closest

to VCCSYN, followed by the 10-µF capacitor, the 10-nH inductor, and finally the 10-Ω resistor to VDD. These traces should be

kept short and direct. Provide an extremely low impedance path to the ground plane for GNDSYN. Bypass GNDSYN to VCCSYN

by a 0.01-µF capacitor located as close as possible to the chip package. For best results, place this capacitor on the backside of

the PCB aligned with the depopulated void on the MSC8122 located in the square defined by positions, L11, L12, L13, M11,

M12, M13, N11, N12, and N13.

VDD

VCCSYN

10Ω 10nH

10 µF

0.01 µF

Figure 34. VCCSYN Bypass

3.3 Connectivity Guidelines

Unused output pins can be disconnected, and unused input pins should be connected to the non-active value, via resistors to

VDDH or GND, except for the following:

• If the DSI is unused (DDR[DSIDIS] is set), HCS and HBCS must pulled up and all the rest of the DSI signals can be

disconnected.

• When the DSI uses synchronous mode, HTA must be pulled up. In asynchronous mode, HTA should be pulled either

up or down, depending on design requirements.

• HDST can be disconnected if the DSI is in big-endian mode, or if the DSI is in little-endian mode and the

DCR[DSRFA] bit is set.

• When the DSI is in 64-bit data bus mode and DCR[BEM] is cleared, pull up HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/

HDBE[1–3] and HWBS[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/PWE[4–7]/PSDDQM[4–7]/PBS[4–7].

• When the DSI is in 32-bit data bus mode and DCR[BEM] is cleared, HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/HDBE[1–3]

must be pulled up.

• When the DSI is in asynchronous mode, HBRST and HCLKIN should either be disconnected or pulled up.

• When the DSI uses sliding window address mode (DCR[SLDWA] = 1), the external HA[11–13] signals must be

connected (tied) to the correct voltage levels so that the host can perform the first access to the DCR. After reset, the

DSI expects full address mode (DCR[SLDWA] = 0). The DCR address in the DSI memory map is 0x1BE000, which

requires the following connections:

— HA11 must be pulled high (1)

— HA12 must be pulled high (1)

— HA13 must be pulled low (0)

• The following signals must be pulled up: HRESET, SRESET, ARTRY, TA, TEA, PSDVAL, and AACK.

• In single-master mode (BCR[EBM] = 0) with internal arbitration (PPC_ACR[EARB] = 0):

— BG, DBG, and TS can be left unconnected.

— EXT_BG[2–3], EXT_DBG[2–3], and GBL can be left unconnected if they are multiplexed to the system bus

functionality. For any other functionality, connect the signal lines based on the multiplexed functionality.

— BR must be pulled up.

— EXT_BR[2–3] must be pulled up if multiplexed to the system bus functionality.

• If there is an external bus master (BCR[EBM] = 1):

— BR, BG, DBG, and TS must be pulled up.

— EXT_BR[2–3], EXT_BG[2–3], and EXT_DBG[2–3] must be pulled up if multiplexed to the system bus

functionality.

• In single-master mode, ABB and DBB can be selected as IRQ inputs and be connected to the non-active value. In other

modes, they must be pulled up.

MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15

Freescale Semiconductor

41

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