SPC5200VVR266B(2006) View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

SPC5200VVR266B
(Rev.:2006)

SDRAM/DDR Memory Controller

Freescale Semiconductor 

Electrical and Thermal Characteristics

The MPC5200B clock generation uses two phase locked loop (PLL) blocks.

• The system PLL (SYS_PLL) takes an external reference frequency and generates the internal

system clock. The system clock frequency is determined by the external reference frequency and

the settings of the SYS_PLL configuration.

• The e300 core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry. The e300

core clock frequency is determined by the system clock frequency and the settings of the

CORE_PLL configuration.

3.2.1 System Oscillator Electrical Characteristics

Table 8. System Oscillator Electrical Characteristics

Characteristic

SYS_XTAL frequency

Oscillator start-up time

Sym

fsys_xtal

tup_osc

Notes Min Typical Max

15.6

33.3

35.0

—

—

10

Unit

MHz

ms

SpecID

O1.1

O1.2

3.2.2 RTC Oscillator Electrical Characteristics

Table 9. RTC Oscillator Electrical Characteristics

Characteristic

Sym

Notes Min Typical Max

RTC_XTAL frequency

frtc_xtal

—

32.768

—

Unit SpecID

kHz

O2.1

3.2.3 System PLL Electrical Characteristics

Table 10. System PLL Specifications

Characteristic

Sym

Notes Min Typical Max

Unit SpecID

SYS_XTAL frequency

SYS_XTAL cycle time

SYS_XTAL clock input jitter

System VCO frequency

System PLL relock time

fsys_xtal

tsys_xtal

tjitter

fVCOsys

tlock

(1)

15.6

33.3

35.0

(1)

66.6

30.0

28.5

(2)

—

—

150

(1)

250

533

800

(3)

—

—

100

MHz

ns

ps

MHz

µs

O3.1

O3.2

O3.3

O3.4

O3.5

NOTES:

1 The SYS_XTAL frequency and PLL Configuration bits must be chosen such that the resulting system frequency,

CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating

frequencies.

2 This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different

types of jitter can exist on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is

rejected. Systemic jitter will be passed into and through the PLL to the internal clock circuitry.

3 Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required

for the PLL lock after a stable VDD and CORE_SYSCLKare reached during the power-on reset sequence. This

specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.

MPC5200B Data Sheet, Rev. 1

Freescale Semiconductor

13

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