SPC5200VVR266B(2006) View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

SPC5200VVR266B
(Rev.:2006)

SDRAM/DDR Memory Controller

Freescale Semiconductor 

Electrical and Thermal Characteristics

Table 13. SYS_XTAL_IN Timing (continued)

Sym

Description

Min Max Units SpecID

t FALL

t DUTY

SYS_XTAL_IN fall time.

SYS_XTAL_IN duty cycle (measured at VM).(2)

—

5.0

ns

A2.3

40.0 60.0 %

A2.4

CVIH SYS_XTAL_IN input voltage high

2.0

—

V

A2.5

CVIL SYS_XTAL_IN input voltage low

—

0.8

V

A2.6

NOTES:

1 CAUTION—The SYS_XTAL_IN frequency and system PLL_CFG[0-6] settings must be chosen such that the

resulting system frequencies do not exceed their respective maximum or minimum operating frequencies. See the

MPC5200B User Manual [1].

2 SYS_XTAL_IN duty cycle is measured at VM.

3.3.3 Resets

The MPC5200B has three reset pins:

• PORRESET - Power on Reset

• HRESET - Hard Reset

• SRESET - Software Reset

These signals are asynchronous I/O signals and can be asserted at any time. The input side uses a Schmitt

trigger and requires the same input characteristics as other MPC5200B inputs, as specified in the DC

Electrical Specifications section. Table 14 specifies the pulse widths of the Reset inputs.

Table 14. Reset Pulse Width

Name

Description

Min Pulse Width

PORRESET

HRESET

SRESET

Power On Reset

Hardware Reset

Software Reset

tVDD_stable+tup_osc+tlock

4 clock cycles

4 clock cycles

Max Pulse

Width

—

—

—

Reference Clock

SYS_XTAL_IN

SYS_XTAL_IN

SYS_XTAL_IN

SpecID

A3.1

A3.2

A3.3

NOTES:

1. For PORRESET the value of the minimum pulse width reflects the power on sequence. If PORRESET is asserted afterwards

its minimum pulse width equals the minimum given for HRESET related to the same reference clock.

2. The tVDD_stable describes the time which is needed to get all power supplies stable.

3. For tlock, refer to the Oscillator/PLL section of this specification for further details.

4. For tup_osc, refer to the Oscillator/PLL section of this specification for further details.

5. Following the deassertion of PORRESET, HRESET and SRESET remain low for 4096 reference clock cycles.

6. The deassertion of HRESET for at least the minimum pulse width forces the internal resets to be active for an additional 4096

clock cycles.

NOTE

As long as VDD is not stable the HRESET output is not stable.

MPC5200B Data Sheet, Rev. 1

16

Freescale Semiconductor

Share Link: