MTV512MV View Datasheet(PDF) - Myson Century Inc
Part Name
Description
Manufacturer
MTV512MV Datasheet PDF : 26 Pages
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PORT5
PORT5
PORT5
PORT5
PORT6
PORT6
PORT6
PORT6
PORT6
PORT6
PORT6
PORT6
PORT7
PORT7
F34h(r/w)
F35h(r/w)
F36h(r/w)
F37h(r/w)
F38h(r/w)
F39h(r/w)
F3Ah(r/w)
F3Bh(r/w)
F3Ch(r/w)
F3Dh(r/w)
F3Eh(r/w)
F3Fh(r/w)
F76h(r/w)
F77h(r/w)
PORT5 (r/w) : Port 5 data input/output value.
PORT6 (r/w) : Port 6 data input/output value.
MTV512M
Preliminary
P54
P55
P56
P57
P60
P61
P62
P63
P64
P65
P66
P67
P76
P77
PWM DAC
Each output pulse width of PWM DAC converter is controlled by an 8-bit register in XFR. The frequency of
PWM clock is 47KHz or 94KHz, selected by PWMF. And the total duty cycle step of these DAC outputs is 253
or 256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to DAC register generates stable high output.
If DIV253=0, the output pulses low at least once even if the DAC register's content is FFH. Writing 00H to DAC
register generates stable low output.
Reg name
addr
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DA0
F20h(r/w)
Pulse width of PWM DAC 0
DA1
F21h(r/w)
Pulse width of PWM DAC 1
DA2
F22h(r/w)
Pulse width of PWM DAC 2
DA3
F23h(r/w)
Pulse width of PWM DAC 3
DA4
F24h(r/w)
Pulse width of PWM DAC 4
DA5
F25h(r/w)
Pulse width of PWM DAC 5
DA0-5 (r/w) : The output pulse width control for DA0-5.
* All of PWM DAC converters are centered with value 80h after power on.
DDC & IIC Interface
i) DDC1/DDC2x Mode, DDCRAM1/DDCRAM2 and SlaveA1/SlaveA2 Block
The MTV512M supports VESA DDC for both D-sub and DVI interfaces through HSCL1/HSDA1 and
HSCL2/HSDA2 pins. The HSCL1/HSDA1 pins access DDCRAM1 by SlaveA1, and the HSCL2/HSDA2 pins
access DDCRAM2 by SlaveA2. The MTV512M enters DDC1 mode for both DDC channels after Reset. In this
mode, VSYNC is used as data clock. The HSCL1/HSCL2 pin should remain at high. The data output to the
HSDA1/HSDA2 pin is taken from a shift register in MTV512M. The shift register automatically fetches EDID
page 11 of 11
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