SST25VF016B View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

SST25VF016B

16 Mbit SPI Serial Flash

Microchip Technology 

SST25VF016B

FIGURE 4-12:

64-KBYTE BLOCK-ERASE SEQUENCE

CE#

MODE 3

SCK MODE 0

0 1 2345 6 78

15 16

23 24 31

SI

D8

ADDR ADDR ADDR

MSB

MSB

SO

HIGH IMPEDANCE

1271 63KBlkEr.0

4.4.9 CHIP-ERASE

The Chip-Erase instruction clears all bits in the device

to FFH. A Chip-Erase instruction will be ignored if any

of the memory area is protected. Prior to any Write oper-

ation, the Write-Enable (WREN) instruction must be exe-

cuted. CE# must remain active low for the duration of

the Chip-Erase instruction sequence. The Chip-Erase

FIGURE 4-13:

CHIP-ERASE SEQUENCE

instruction is initiated by executing an 8-bit command,

60H or C7H. CE# must be driven high before the instruction

is executed. The user may poll the Busy bit in the software

status register or wait TCE for the completion of the

internal self-timed Chip-Erase cycle. See Figure 4-13

for the Chip-Erase sequence.

CE#

MODE 3

SCK MODE 0

0 1 2345 6 7

SI

60 or C7

MSB

SO

HIGH IMPEDANCE

1271 ChEr.0

DS20005044C-page 14

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 2015 Microchip Technology Inc.

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