SST25VF016B View Datasheet(PDF) - Microchip Technology
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SST25VF016B Datasheet PDF : 30 Pages
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SST25VF016B
4.4.10 READ-STATUS-REGISTER (RDSR)
The Read-Status-Register (RDSR) instruction allows
reading of the status register. The status register may
be read at any time even during a Write (Program/
Erase) operation. When a Write operation is in prog-
ress, the Busy bit may be checked before sending any
new commands to assure that the new commands are
properly received by the device. CE# must be driven
low before the RDSR instruction is entered and remain
low until the status data is read. Read-Status-Register
is continuous with ongoing clock cycles until it is termi-
nated by a low to high transition of the CE#. See Figure
4-14 for the RDSR instruction sequence.
FIGURE 4-14:
READ-STATUS-REGISTER (RDSR) SEQUENCE
CE#
MODE 3 0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
SCK MODE 0
SI
05
MSB
HIGH IMPEDANCE
SO
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
Status
Register Out
1271 RDSRseq.0
4.4.11 WRITE-ENABLE (WREN)
The Write-Enable (WREN) instruction sets the Write-
Enable-Latch bit in the Status Register to 1 allowing
Write operations to occur. The WREN instruction must
be executed prior to any Write (Program/Erase) opera-
tion. The WREN instruction may also be used to allow
execution of the Write-Status-Register (WRSR) instruc-
tion; however, the Write-Enable-Latch bit in the Status
Register will be cleared upon the rising edge CE# of the
WRSR instruction. CE# must be driven high before the
WREN instruction is executed.
FIGURE 4-15:
WRITE ENABLE (WREN) SEQUENCE
CE#
MODE 3
SCK MODE 0
0 1 2345 6 7
SI
06
MSB
SO
HIGH IMPEDANCE
1271 WREN.0
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