AT89C5131A-M(2005) View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT89C5131A-M
(Rev.:2005)

8-bit Flash Microcontroller with Full Speed USB Device

Atmel Corporation 

Figure 6. Crystal Connection

C1

C2

VSS

X1

Q

X2

PLL

PLL Description

The AT89C5130A/31A-M PLL is used to generate internal high frequency clock (the

USB Clock) synchronized with an external low-frequency (the Peripheral Clock). The

PLL clock is used to generate the USB interface clock. Figure 7 shows the internal

structure of the PLL.

The PFLD block is the Phase Frequency Comparator and Lock Detector. This block

makes the comparison between the reference clock coming from the N divider and the

reverse clock coming from the R divider and generates some pulses on the Up or Down

signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON

register is used to enable the clock generation. When the PLL is locked, the bit PLOCK

in PLLCON register (see Figure 7) is set.

The CHP block is the Charge Pump that generates the voltage reference for the VCO by

injecting or extracting charges from the external filter connected on PLLF pin (see

Figure 8). Value of the filter components are detailed in the Section “DC

Characteristics”.

The VCO block is the Voltage Controlled Oscillator controlled by the voltage VREF pro-

duced by the charge pump. It generates a square wave signal: the PLL clock.

Figure 7. PLL Block Diagram and Symbol

OSC

CLOCK

N divider

N3:0

PLLCON.1

PLLEN

PLLF

Up

PFLD

Vref

CHP

Down

PLOCK

PLLCON.0

R divider

R3:0

VCO

USBclk = -O-----S----C----c----l--k----×-----(--R------+-----1----)

N+1

Figure 8. PLL Filter Connection

PLLF

R

C1

VSS

C2

VSS

USB Clock

USB

CLOCK

USB Clock Symbol

The typical values are: R = 100 Ω, C1 = 10 nf, C2 = 2.2 nF.

14 AT89C5130A/31A-M

4337C–USB–02/05

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