AT89C5131A-M(2005) View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
AT89C5131A-M Datasheet PDF : 184 Pages
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4337C–USB–02/05
AT89C5130A/31A-M
Table 15. CKCON1 (S:AFh)
Clock Control Register 1
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
SPIX2
Bit
Bit Number Mnemonic Description
7-1
-
Reserved
The value read from this bit is always 0. Do not set this bit.
SPI Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
0
SPIX2 this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Reset Value = 0000 0000b
Table 16. PLLCON (S:A3h)
PLL Control Register
Table 17.
7
6
5
4
3
2
1
0
-
-
-
-
-
EXT48
PLLEN
PLOCK
Bit
Bit Number Mnemonic Description
7-3
-
Reserved
The value read from this bit is always 0. Do not set this bit.
External 48 MHz Enable Bit
2
EXT48
Set this bit to bypass the PLL and disable the crystal oscillator.
Clear this bit to select the PLL output as USB clock and to enable the crystal
oscillator.
PLL Enable Bit
1
PLLEN Set to enable the PLL.
Clear to disable the PLL.
PLL Lock Indicator
0
PLOCK Set by hardware when PLL is locked.
Clear by hardware when PLL is unlocked.
Reset Value = 0000 0000b
Table 18. PLLDIV (S:A4h)
PLL Divider Register
Table 19.
7
6
5
4
3
2
1
0
R3
R2
R1
R0
N3
N2
N1
N0
Bit
Bit Number Mnemonic Description
7-4
R3:0 PLL R Divider Bits
17
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