MU9C8248QEC View Datasheet(PDF) - Music Semiconductors

Part Name

Description

Manufacturer

MU9C8248QEC

FDDI SRT Interface

Music Semiconductors 

MU9C8248

INSTRUCTION SET DESCRIPTION (CONT’D)

instruction of the routine and execution of the routine is stopped

after this instruction has been executed. The length of the

instruction is determined by l. For the coding of the l bits refer

to Table 2.

Instruction:

Move data from address 1aaaaaaB to

DQ15–DQ0.

Binary Op Code: 0100 rrrr r1aa aaaa 0ce1 slll

r Reserved

a Address

c The state of /CM

e The state of /EC

s Stop routine

l Instruction length

The “Move data from address 1aaaaaaB to DQ15–DQ0”

instruction places the contents of the address specified by the

“a” bits on the DQ15–DQ0 lines. The control outputs /CM and

/EC at the falling edge of /E for this cycle are defined by c and

e. If s is set HIGH, the instruction is the last instruction of the

routine and execution of the routine is stopped after this

instruction has been executed. The length of the instruction is

determined by l. For the coding of the l bits refer to Table 2.

Instruction:

Move data from DQ15–DQ0 to address

1aaaaaaB.

Binary Op Code: 0101 rrrr r1aa aaaa 1ce1 slll

r Reserved

a Address

c The state of /CM

e The state of /EC

s Stop routine

l Instruction length

Instruction:

Move data from DQ15–DQ0 to the FIFO.

Binary Op Code: 0111 rrrr rrrr rrrr 1ce1 slll

r Reserved

c The state of /CM

e The state of /EC

s Stop routine

l Instruction length

This instruction places the values on the DQ15–DQ0 lines into

the FIFO. The control outputs /CM and /EC at the falling edge

of /E for this cycle are defined by c and e. If s is set HIGH, the

instruction is the last instruction of the routine and execution of

the routine is stopped after this instruction has been executed.

The length of the instruction is determined by l. For the coding

of the l bits refer to Table 2.

lll

/E HIGH /E LOW Instruction Length

000B

001B

010B

011B

100B

1 MCLK

1 MCLK

1 MCLK

2 MCLK

3 MCLK

1 MCLK

2 MCLK

3 MCLK

1 MCLK

1 MCLK

2 MCLK

3 MCLK

4 MCLK

3 MCLK

4 MCLK

Note: An 300XH instruction executed after an not 300XH

instruction takes one extra MCLK cycle.

Table 2: Instruction Length

This instruction places the values on the DQ15–DQ0 lines in

the address specified by the “a” bits. The control outputs /CM

and /EC at the falling edge of /E for this cycle are defined by c

and e. If s is set HIGH, the instruction is the last instruction of

the routine and execution of the routine is stopped after this

instruction has been executed. The length of the instruction is

determined by l. For the coding of the l bits refer to Table 2.

Instruction:

Move data from the FIFO to DQ15–DQ0.

Binary Op Code: 0110 rrrr rrrr rrrr 0ce1 slll

r Reserved

c The state of /CM

e The state of /EC

s Stop routine

l Instruction length

The “Move data from the FIFO to DQ15–DQ0” instruction

places the contents of the next FIFO location on the

DQ15–DQ0 lines. The control outputs /CM and /EC at the

falling edge of /E for this cycle are defined by c and e. If s is set

HIGH, the instruction is the last instruction of the routine and

execution of the routine is stopped after this instruction has

been executed. The length of the instruction is determined by l.

For the coding of the l bits refer to Table 2.

Rev. 2.5 Web

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