IS43TR16640A-125KBL View Datasheet(PDF) - Unspecified
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IS43TR16640A-125KBL Datasheet PDF : 71 Pages
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IS43TR16640A, IS43TR81280A
2.4.1. CKE Truth Table
Current State2
Power-Down
CKE
Previous Cycle1 (N-1)
L
L
Current Cycle1(N)
L
H
Command (N)3
RAS#, CAS#, WE#,
CS#
X
DESELECT or NOP
Action (N)3
Maintain Power-Down
Power-Down Exit
Notes
14,15
11,14
L
Self-Refresh
L
L
X
Maintain Self-Refresh
15,16
H
DESELECT or NOP
Self-Refresh Exit
8,12,16
Bank(s) Active
H
L
DESELECT or NOP
Active Power-Down Entry
11,13,14
Reading
H
L
DESELECT or NOP
Power-Down Entry
11,13,14,17
Writing
H
L
DESELECT or NOP
Power-Down Entry
11,13,14,17
Precharging
H
L
DESELECT or NOP
Power-Down Entry
11,13,14,17
Refreshing
H
L
DESELECT or NOP
Precharge Power-Down Entry
11
All Bank Idle
H
L
DESELECT or NOP
Precharge Power-Down Entry
11,13,14,18
H
L
REFRESH
Self-Refresh
9.13.18
Notes:
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
2. Current state is defined as the state of the DDR3 SDRAM immediately prior to clock edge N.
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N), ODT is not included here.
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self-Refresh.
6. CKE must be registered with the same value on tCKEmin consecutive positive clock edges. CKE must remain at the valid input level the entire time it
takes to achieve the tCKEmin clocks of registeration. Thus, after any CKE transition, CKE may not transition from its valid level during the time
period of tIS + tCKEmin + tIH.
7. DESELECT and NOP are defined in the Command Truth Table.
8. On Self-Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXS period. Read or ODT commands
may be issued only after tXSDLL is satisfied.
9. Self-Refresh mode can only be entered from the All Banks Idle state.
10. Must be a legal command as defined in the Command Truth Table.
11. Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
12. Valid commands for Self-Refresh Exit are NOP and DESELECT only.
13. Self-Refresh cannot be entered during Read or Write operations.
14. The Power-Down does not perform any refresh operations.
15. “X” means “don’t care“ (including floating around VREF) in Self-Refresh and Power-Down. It also applies to Address pins.
16. VREF (Both Vref_DQ and Vref_CA) must be maintained during Self-Refresh operation.VrefDQ supply may be turned OFF and VREFDQ may take
any value between VSS and VDD during Self Refresh operation, provided that VrefDQ is valid and stable prior to CKE going back High and that first
Write operation or first Write Leveling Activity may not occur earlier than 512 nCK after exit from Self Refresh.
17. If all banks are closed at the conclusion of the read, write or precharge command, then Precharge Power-Down is entered, otherwise Active Power-
Down is entered.
18. ‘Idle state’ is defined as all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress, CKE is high, and all timings from previous
operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) as well as all Self-Refresh exit and Power-Down Exit parameters are
satisfied (tXS, tXP, tXPDLL, etc).
2.4.2 No Operation (NOP) Command
The No operation (NOP) command is used to instruct the selected DDR3 SDRAM to perform a NOP ( CS# low and
RAS#,CAS#,WE# high). This prevents unwanted commands from being registered during idle or wait states. Operations
already in progress are not affected.
2.4.3 Deselect(DES) Command
The Deselect function (CS# HIGH) prevents new commands from being executed by the DDR3 SDRAM. The DDR3
SDRAM is effectively deselected. Operations already in progress are not affected.
Integrated Silicon Solution, Inc. – www.issi.com –
20
Rev. 00A
04/16/2012
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