IS43TR16640A-125KBL View Datasheet(PDF) - Unspecified
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Description
Manufacturer
IS43TR16640A-125KBL Datasheet PDF : 71 Pages
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IS43TR16640A, IS43TR81280A
4. AC & DC INPUT MEASUREMENT LEVELS
4.1. AC and DC Logic Input Levels for Single-Ended Signals
4.1.1 AC and DC Input Levels for Single-Ended Command and Address Signals
Symbol
Parameter
DDR3-800/1066/1333/1600
Min
Max
Unit
Note
VIH.DQ(DC100)
DC input logic high
Vref + 0.100
VDD
V
1
VIL.DQ(DC100)
DC input logic low
VSS
Vref - 0.100
V
1
VIH.DQ(AC175)
AC input logic high
Vref + 0.175
Note 2
V
1,2
VIL.DQ(AC175)
AC input logic low
Note 2
Vref - 0.175
V
1,2
VIH.CA(AC150)
AC input logic high
Vref + 0.150
Note2
V
1,2
VIL.CA(AC150)
AC input logic low
Note2
Vref - 0.150
V
1,2
VREFCA(DC)
Reference Voltage for ADD, CMD inputs
0.49 * VDD
0.51 * VDD
V
3,4
Notes:
1. For input only pins except RESET.Vref=VrefCA(DC)
2. See "Overshoot and Undershoot Specifications"
3. The ac peak noise on Vref may not allow Vref to deviate from Vref(DC) by more than +/- 0.1% VDD.
4. For reference: approx. VDD/2 +/- 15mV.
5. To allow VREFCA margining, all DRAM Command and Address Input Buffers MUST use external VREF (provided by system) as the input for their
VREFCA pins. All VIH/L input level MUST be compared with the external VREF level at the 1st stage of the Command and Address input buffer
4.1.2 AC and DC Logic Input Levels for Single-Ended Signals & DQ and DM
Symbol
VIH.DQ(DC100)
VIL.DQ(DC100)
VIH.DQ(AC175)
VIL.DQ(AC175)
VIH.DQ(AC150)
VIL.DQ(AC150)
VREFDQ(DC)
Parameter
DC input logic high
DC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic low
Reference Voltage for DQ,
DM inputs
DDR3-800/1066
Min.
Vref +0.100
VSS
Vref +0.175
Note2
Vref +0.150
Note2
Max.
VDD
Vref -0.100
Note2
Vref -0.175
Note2
Vref -0.150
0.49 *VDD 0.51 *VDD
DDR3-1333/1600
Min.
Vref +0.100
VSS
Vref +0.150
Note2
Vref +0.150
Note2
Max.
VDD
Vref -0.100
Note2
Vref -0.150
Note2
Vref -0.150
0.49 *VDD 0.51 *VDD
Unit Note
V
1
V
1
V 1,2,5
V 1,2,5
V 1,2,5
V 1,2,5
V
3,4
VREFDQ_t(DC)
Reference Voltage for
trained DQ, DM inputs
0.45 *VDD
0.55 *VDD
0.45 *VDD
0.55 *VDD
V
3,4,
6,7
Notes:
1. For input only pins except RESET#. Vref = VrefDQ(DC)
2. See "Overshoot and Undershoot Specifications"
3. The ac peak noise on Vref may not allow Vref to deviate from Vref(DC) by more than ± 0.1% VDD.
4. For reference: approx. VDD/2 ±15mV.
5. Single-ended swing requirement for DQS-DQS#, is 350mV (peak to peak). Differential swing requirement for DQS-DQS#, is 700mV (peak to peak)
6. VRefDQ training is performed only during system boot. Once the training is completed and an optimal VRefDQ_t(DC) voltage level is identified, the
optimal VRefDQ_t(DC) voltage level will be used during system runtime. During VRefDQ training, VRefDQ is swept from 40% of VDD to 60% of VDD to
find the optimal VRefDQ_t(DC) voltage level; and once the optimal VRefDQ_t(DC) is set, it must stay within ±1% of its set value as well as not be less
than 45% of VDD or exceed 55% of VDD. VIH.DQ(AC)min/VIL.DQ(AC)max = Optimal VRefDQ_t(DC) ±AC Level, where "AC Level" is the actual AC
voltage level per DDR3 speed bins as specified in JESD79-3 specification. After VRefDQ training is completed and the optimal VRefDQ_t(DC) is set, the
Memory Controller provides the DRAM device a valid write window. Through DQS placement optimization and VRefDQ centering, the valid write window
is optimized for both input voltage margin and tDS+tDH window for the DRAM receiver. The DRAM device supports the use of the above techniques to
optimize the write timing and voltage margin, as long as the technique does not create any DIMM failures due to DRAM input voltage and/or timing spec
violations as defined in JESD79-3 specification.
7. To allow VREFDQ margining, all DRAM Data Input Buffers MUST use external VREF (provided by system) as the input for their VREFDQ pins. All
VIH/L input level MUST be compared with the external VREF level at the 1st stage of the Data input buffer.
Integrated Silicon Solution, Inc. – www.issi.com –
29
Rev. 00A
04/16/2012
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