ST7FLITEU05B3 View Datasheet(PDF) - STMicroelectronics
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Description
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ST7FLITEU05B3 Datasheet PDF : 115 Pages
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ST7LITEU05 ST7LITEU09
RESET SEQUENCE MANAGER (Cont’d)
7.3.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated RON weak pull-up resistor.
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.
A RESET signal originating from an external
source must have a duration of at least th(RSTL)in in
order to be recognized (see Figure 17). This de-
tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
7.3.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until VDD is over the minimum
level specified for the selected fCLKIN frequency.
Figure 17. RESET Sequences
VDD
VIT+(LVD)
VIT-(LVD)
A proper reset signal for a slow rising VDD supply
can generally be provided by an external RC net-
work connected to the RESET pin.
7.3.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■ Power-On RESET
■ Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when VDD<VIT+ (rising edge) or
VDD<VIT- (falling edge) as shown in Figure 17.
The LVD filters spikes on VDD larger than tg(VDD) to
avoid parasitic resets.
7.3.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 17.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least tw(RSTL)out.
RUN
LVD
RESET
ACTIVE PHASE
RUN
EXTERNAL
RESET
ACTIVE
PHASE
RUN
WATCHDOG
RESET
ACTIVE
PHASE
RUN
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
th(RSTL)in
tw(RSTL)out
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 512 TCPU)
VECTOR FETCH
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