K4B4G1646Q View Datasheet(PDF) - Samsung

Part Name

Description

Manufacturer

K4B4G1646Q

4Gb Q-die DDR3L SDRAM Olny x16 96FBGA with Lead-Free & Halogen-Free (RoHS compliant) 1.35V

Samsung 

K4B4G1646Q

datasheet

8.3 AC & DC Logic Input Levels for Differential Signals

8.3.1 Differential signals definition

VIH.DIFF.AC.MIN

tDVAC

VIH.DIFF.MIN

Preliminary Rev. 0.5

DDR3L SDRAM

0.0

VIL.DIFF.MAX

VIL.DIFF.AC.MAX

half cycle

tDVAC

time

Figure 1. Definition of differential ac-swing and "time above ac level" tDVAC

8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)

[ Table 11 ] Differential AC & DC Input Levels

DDR3-800/1066/1333/1600

Symbol

Parameter

1.35V

1.5V

unit NOTE

min

max

min

max

VIHdiff

differential input high

+0.18

NOTE 3

+0.20

NOTE 3

V

1

VILdiff

differential input low

NOTE 3

-0.18

NOTE 3

-0.20

V

1

VIHdiff(AC) differential input high ac 2 x (VIH(AC) - VREF)

NOTE 3

2 x (VIH(AC) - VREF)

NOTE 3

V

2

VILdiff(AC) differential input low ac

NOTE 3

2 x (VIL(AC) - VREF)

NOTE 3

2 x (VIL(AC) - VREF) V

2

NOTE :

1. Used to define a differential signal slew-rate.

2. for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS use VIH/VIL(AC) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group,

then the reduced level applies also here.

3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended sig-

nals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undersheet Specification"

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